Samsung Electronics and SK Hynix used this year’s Future of Memory and Storage conference in Santa Clara to lay out competing answers to a problem that has quietly become the biggest constraint on artificial intelligence: not raw processing power, but the speed at which data can move between a chip and its memory. Both companies argued that the fix is to stack memory in three dimensions and move it physically closer to the processor, reshaping how AI accelerators are built.
The dueling roadmaps, presented in early August 2026, mark a shift in the memory business. For years the competition centered on how many bits a chip could hold and how fast a single stack could run. Now it is turning toward system architecture — where the memory sits, how far the data has to travel, and how much power that movement consumes. As generative systems give way to more demanding agentic and physical AI workloads, that data-movement penalty has become the factor that limits overall performance.
Samsung’s zHBM stacks memory on top of the accelerator
Samsung’s centerpiece was the industry’s first concept models of two 3D architectures it calls zHBM and zNAND-O, previewed alongside a 400-plus-layer flash chip during a keynote on 3D innovation in memory and storage, according to the company’s official announcement from the show. Rather than placing high-bandwidth memory beside the processor, zHBM stacks it vertically above the AI accelerator, shortening the distance data must travel. Samsung says a next-generation interface built around zHBM could deliver roughly eight times the performance of a future HBM5 generation, while new wafer-bonding techniques push memory density more than tenfold, improve energy efficiency threefold and cut thermal resistance by more than half.
Those are targets for a concept, not specifications for a shipping part, and the framing has evolved quickly. When Samsung first described zHBM at a February industry event, it pitched the design as four times faster than today’s HBM4 standard at a quarter of the power, a comparison that industry analysts tracked into the Santa Clara reveal. The company also positioned zNAND-O, a low-latency flash design, for edge devices that need to process data locally in real time.
SK Hynix bets on tiered memory instead of a single stack
SK Hynix took a different route to the same goal. Instead of one taller stack, it outlined a tiered system that inserts new layers between the fastest memory and long-term storage. Its High Bandwidth Flash effort, developed with SanDisk under an Open Compute Project working group, aims to create a storage tier that sits between HBM and solid-state drives to hold the enormous data sets that large AI inference jobs require. A companion design the company calls Inference Memory Tiering Expansion adds a layer of CXL memory to the traditional hierarchy, predicting which data the faster tiers will need and prefetching it — an approach a detailed account of both companies’ plans reported could improve inference efficiency by roughly 36 percent over conventional designs.
The contrast captures the strategic split now running through the memory industry. Samsung is betting that bonding memory directly onto the accelerator wins on bandwidth and power. SK Hynix is betting that a smarter hierarchy of memory types, orchestrated in software, wins on capacity and cost for the inference-heavy workloads that dominate commercial AI.
How memory became AI’s choke point
The reason both companies are reorganizing their entire roadmaps around this problem is that the memory, not the logic, increasingly sets the ceiling on AI systems. A modern accelerator can perform far more calculations per second than its attached memory can feed it, so the processor spends cycles waiting for data. Widening that pipe has traditionally meant adding more HBM stacks beside the chip, but each stack consumes power and board space and still forces signals across a comparatively long path.
High-bandwidth memory is also scarce. Samsung reached mass production of its HBM4 generation early in 2026 and began shipping samples of the follow-on HBM4E in the spring, milestones it detailed when it announced the first commercial HBM4. Even so, demand has outrun supply across the industry, with much of the year’s output committed to a handful of large buyers well in advance. Stacking memory vertically is partly an attempt to wring more performance from each unit of that constrained capacity.
What stacked memory would change for AI data centers
If the concepts reach production, the payoff would show up first in power and heat. Data centers running large AI clusters are increasingly limited by how much electricity they can draw and how much heat they can remove, so a memory design that moves the same data using a fraction of the energy directly expands how much computing a given facility can house. Vertical stacking also frees the board space that side-by-side memory occupies, allowing more accelerators in the same rack.
Both roadmaps remain previews rather than products, and the manufacturing challenges of bonding memory onto hot, power-dense processors are significant. What the Santa Clara reveals establish is the direction of travel: the next contest among the world’s largest memory makers will be won less by how many bits a chip holds and more by how cleverly those bits are arranged around the processor that needs them.
This article was produced with AI assistance and reviewed by the Morning Overview editorial team.
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