The chip race just moved to backside power delivery, the trick meant to squeeze more out of the smallest transistors

For decades, the wiring that delivers electricity to a chip’s transistors and the wiring that carries its signals have shared the same side of the silicon, stacked in increasingly cramped layers above the transistors themselves. That arrangement is now being pulled apart, with power delivery moving to the back of the wafer entirely, a manufacturing shift that chipmakers are betting will unlock meaningful gains in speed and efficiency just as shrinking transistors further has become brutally difficult.

What Backside Power Delivery Actually Changes

Backside power delivery separates a chip’s power network from its signal-routing network by moving the power rails to the underside of the wafer, opposite the transistors, instead of stacking everything above them as in a conventional design. Signal wires keep their usual position on the front side, while a distinct set of metal layers on the back handles the job of feeding electricity to each transistor. The split reduces congestion in the front-side wiring stack, which in modern chips has grown to a dozen or more layers, and it shortens the physical distance power has to travel to reach a transistor, cutting resistance losses along the way.

Why Traditional Front-Side Wiring Ran Out of Room

As transistors have shrunk generation after generation, the wires connecting them have not shrunk as easily, because thinner wires carry current less efficiently and generate more resistive heat. That mismatch created a bottleneck: the transistors themselves kept getting smaller and faster, but the wiring meant to power and connect them became a larger share of a chip’s total delay and energy loss. Engineers had already stacked signal and power wiring into increasingly tall towers of metal layers to cope, but that approach was approaching its practical limit, both in terms of manufacturing complexity and the sheer amount of space consumed above the transistor layer.

TSMC’s A16 Process and Its Place in the Roadmap

Taiwan Semiconductor Manufacturing Company has folded its own version of backside power delivery into the process node it calls A16, positioning the technology as a companion to the company’s continued transition toward gate-all-around transistor architecture. According to industry reporting on TSMC’s roadmap, the company has discussed A16 as a node aimed particularly at high-performance computing customers, where the density and power-delivery gains matter most for large, power-hungry processors. The move places TSMC alongside rivals that have pursued the same basic concept under different names, each racing to be first to ship it in volume for a customer willing to redesign around the new manufacturing flow.

How Rivals Have Approached the Same Problem

TSMC is not alone in pursuing backside power delivery. Intel has built its own version, which it calls PowerVia, into its most advanced manufacturing nodes, framing it as a centerpiece of the company’s effort to regain process-technology leadership. Samsung has likewise discussed backside power networks for its future nodes. The broader industry convergence on the same idea, arrived at independently by competing manufacturers, is itself a signal of how significant a limitation front-side-only wiring had become, since foundries rarely commit to a manufacturing overhaul this disruptive unless the alternative has clearly stopped scaling.

The Manufacturing Challenge of Building Power Rails on the Back

Moving power delivery to the back of the wafer is not simply a matter of relocating existing wiring. It requires thinning the wafer dramatically after the front-side transistor layers are complete, then precisely aligning and etching a new set of connections from the back side down to the transistor layer without damaging the delicate structures already built. That process, combined with the gate-all-around transistor designs described in broader research on multigate device architecture, adds cost and manufacturing steps that only the most advanced foundries can currently execute reliably at high yield, which is part of why backside power delivery has arrived first at the leading edge of the industry rather than in mainstream, older process nodes.

What the Shift Means for Future Chips

For chip designers, backside power delivery promises lower voltage drop across a chip, meaning transistors receive more consistent power even under heavy load, along with freed-up space on the front side that can be used for additional signal routing or higher transistor density. Those gains matter most for the largest, most power-intensive processors, including the accelerators used in data centers and high-end computing, where even modest efficiency improvements translate into meaningful reductions in energy use at scale. As more foundries bring the technique into production, it is likely to become a standard feature of leading-edge chip manufacturing rather than a differentiator unique to any single company. The timing is not a coincidence: backside power delivery is arriving at roughly the same moment the industry is shifting away from the finFET transistor design that has dominated chipmaking for more than a decade, toward gate-all-around structures that wrap a transistor’s gate fully around a stacked set of nanosheet channels, a shift described in general terms in research covering multigate device architecture. Pairing that transistor shift with a reworked power-delivery network lets manufacturers optimize both halves of the problem at once rather than bolting one new technique onto an otherwise unchanged process, since foundries tend to bundle their most disruptive manufacturing changes into the same node transition rather than qualifying an entirely new process with customers twice in quick succession.

This article was produced with the assistance of AI and reviewed by Morning Overview editors prior to publication.

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