For decades, chipmakers squeezed more transistors onto processors by shrinking them sideways. That playbook is running out of room. Now, a team of engineers has demonstrated a different strategy: stacking fully functional transistor layers vertically on the same wafer, separated by silicon membranes just 10 nanometers thick, thin enough that roughly 10,000 of them would fit across the width of a human hair.
The work, published in Nature in early 2026, describes a wafer-scale roll-transfer-printing process that produces single-crystalline silicon nanomembranes and then builds complementary junctionless transistors on them, one tier at a time, at temperatures no higher than 400 degrees Celsius. That temperature ceiling is critical: it means each new layer can be fabricated without melting or warping the circuits already finished below. The result is a monolithic stack, not a sandwich of separately manufactured wafers bonded together after the fact.
Why going vertical matters now
Transistor scaling has followed a remarkably consistent pattern since the 1960s, but the most advanced nodes, currently at 2 and 3 nanometers, are approaching physical limits where atoms themselves become obstacles. The semiconductor industry has not been idle. TSMC, Samsung, and Intel are all pursuing gate-all-around architectures and complementary FET (CFET) designs that stack n-type and p-type transistors within a single device. But those approaches still operate within a fundamentally planar framework, adding vertical complexity at the transistor level rather than stacking entire circuit layers.
True three-dimensional chip stacking has been attempted before, most commonly by drilling through-silicon vias (TSVs) through thick wafer substrates to connect one layer to the next. In a separate, earlier project from December 2024, MIT researchers detailed a related but distinct effort to grow layered chips, explaining how thick substrates consume valuable vertical space and how the drilling process limits how many layers can be aligned before manufacturing yield collapses. Hybrid bonding, used commercially today in products like AMD’s 3D V-Cache, improves on TSVs but still joins separately fabricated chiplets rather than building circuits monolithically.
The roll-transfer approach sidesteps both problems. By replacing thick silicon floors with membranes that are orders of magnitude thinner, it opens a path to stacking many more active layers in the same vertical envelope.
Three independent paths to the same destination
The Nature roll-transfer paper is not an isolated result. At least two other research groups have reached similar conclusions through different fabrication methods, reinforcing the idea that monolithic 3D integration is becoming technically viable.
A separate Nature study demonstrated growth-based integration using single-crystal two-dimensional semiconductor layers. Instead of transferring pre-made membranes, this method grows new active material directly on top of existing circuitry at temperatures compatible with the devices underneath. Meanwhile, a Nature Communications paper showed that vertical sidewall transistors built from molybdenum disulfide (MoS₂) through a repeatable layer-by-layer lamination process can stack multiple devices without consuming any additional chip footprint beyond the bottom device’s planar area.
Each method uses different materials and fabrication flows, but all three converge on the same principle: build upward with ultra-thin active layers, skip the bulky substrates, and keep processing temperatures low enough to protect what is already built.
From university cleanroom to commercial foundry
Lab demonstrations are one thing. Proving that a process can survive contact with real manufacturing infrastructure is another. Carnegie Mellon’s NEXUS Research Group took a step in that direction when it presented results at IEDM, the semiconductor industry’s premier device conference, showing a foundry-compatible monolithic 3D process run at SkyWater Technology on 200 mm wafers using 90 and 130 nm nodes.
That work integrated silicon CMOS, resistive RAM (RRAM), and carbon nanotube field-effect transistors in the back-end-of-line at 415 degrees Celsius or below. The significance is not the node size, which is several generations behind the leading edge, but the venue: a commercial foundry running standard equipment. It suggests that at least the basic mechanics of low-temperature vertical stacking can coexist with existing manufacturing steps.
The hard problems that remain
None of these demonstrations are close to producing chips a consumer could buy, and several substantial gaps stand between the lab and the factory floor.
Yield and defect density. No publicly available data from the SkyWater runs details yield rates, defect densities, or variability across full wafers. A foundry-compatible process on 200 mm wafers at older nodes is a long way from the 300 mm, sub-7 nm production lines where leading-edge chips are made. Whether the roll-transfer method or the growth-based 2D approach can meet the defect thresholds that high-volume manufacturing demands, especially when dozens of layers would need to be stacked with tight alignment, is an open question.
Performance benchmarks. Direct comparisons between the different stacking methods do not yet exist. The Nature papers report device-level electrical characteristics such as current-voltage curves and switching behavior, but head-to-head data on switching speed, leakage current, or energy per operation across the three approaches has not been published. Without those numbers, it is difficult to judge which pathway suits which application, whether that is high-performance processors, dense memory, or low-power edge devices.
Thermal management. Chips in data centers and automotive systems endure years of continuous heat cycling. The 10 nm silicon membranes at the heart of the roll-transfer process are far thinner than any production silicon layer in use today, and published durability data under real-world thermal stress remains limited. How many vertical tiers can be stacked before heat dissipation becomes unmanageable, and how these delicate layers respond to electromigration and packaging stress, has not been answered definitively.
Design tool readiness. Today’s electronic design automation (EDA) tools assume essentially planar layouts with limited vertical connectivity. Moving to true three-dimensional logic and memory would require new design rules, placement strategies, and verification methods. None of the current demonstrations show a full system-on-chip implemented with these new degrees of freedom; they remain at the level of device arrays and small-scale circuits.
Where this fits in the scaling roadmap
The evidence as of mid-2026 supports a cautious but genuine shift in what is possible. Researchers have convincingly shown that ultra-thin silicon membranes, 2D semiconductors, and laminated MoS₂ structures can host functional transistors in vertically stacked configurations, fabricated without the thick substrates and TSVs that limited earlier 3D attempts. The Carnegie Mellon work adds a practical data point: at least on mature nodes, these techniques can run on commercial foundry equipment.
What remains to be shown is how these methods hold up against the unforgiving economics of mass production, the complexity of full system design, and the harsh operating conditions of real-world deployment. The major foundries are watching closely, but none have publicly committed to adopting any of these specific approaches for production nodes. For now, the work marks a credible engineering path beyond the end of conventional transistor scaling. Whether it becomes the path will depend on answers to questions the lab results, impressive as they are, have not yet addressed.
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*This article was researched with the help of AI, with human editors creating the final content.
