When Jensen Huang walked onto the CES stage in Las Vegas in January 2025, he had a single number he wanted the audience to remember: six. That is how many new Nvidia chips, fabricated by TSMC, make up the company’s next-generation AI superchip platform. And as of that keynote, Huang said, the platform had entered “full production,” meaning volume shipments to data-center customers were underway, not just promised on a roadmap slide.
The announcement, reported by Taiwan’s CNA wire service and independently confirmed by Reuters, marked a turning point in the GPU race. Frontier AI labs building models with trillions of parameters need hardware that did not exist two years ago, and Nvidia is betting that a multi-die design can deliver the compute density those projects require while keeping manufacturing yields high enough to ship at scale.
Why six chips instead of one
Previous Nvidia flagship GPUs, from the A100 to the H100 to the B200, were each built around a single large die. The physics of chipmaking punish size: the bigger the piece of silicon, the more likely a random defect ruins the whole thing. By splitting the design across six separate dies, Nvidia and TSMC can manufacture each one at higher yield rates, then connect them using advanced packaging techniques such as TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) technology.
This approach also gives Nvidia architectural flexibility. Different dies can handle different jobs: some optimized for floating-point math, others for memory control or chip-to-chip communication. Mixing functional blocks, and potentially mixing process nodes, lets engineers tune each piece of the system without being locked into a single design compromise. It is the same chiplet philosophy AMD has used in its EPYC server processors, now applied to the most power-hungry AI accelerators on the planet.
What “full production” actually signals
In semiconductor language, “full production” is a specific and deliberate phrase. It means a product has cleared qualification, yields are stable enough for volume manufacturing, and units are shipping to paying customers. It is a step beyond “sampling” (sending test chips to partners) and beyond “production ramp” (gradually increasing output). Huang chose those words on a globally broadcast stage, in front of investors, analysts, and competitors. Because Nvidia is publicly traded, a material misstatement about production status would carry securities liability, so the company’s legal and investor-relations teams would have vetted the language before Huang said it.
For hyperscale cloud providers and sovereign AI programs planning massive training clusters, the distinction matters. “Full production” is a green light to place orders against real inventory rather than waiting on an uncertain timeline. Several of Nvidia’s largest customers, including Microsoft, Meta, and Oracle, had already disclosed billions of dollars in planned AI infrastructure spending through their 2025 earnings calls, and the production milestone gives those commitments a concrete hardware foundation.
What Nvidia has not yet disclosed
Huang’s keynote confirmed the platform’s existence and its production status, but it left significant gaps. Nvidia has not publicly released detailed specifications for the six-die module: interconnect bandwidth between dies, total memory capacity, peak floating-point throughput, or thermal design power. Without those numbers, data-center operators cannot finalize rack layouts, power distribution, or cooling-plant sizing for facilities scheduled to come online in the coming months.
Pricing and packaging details are also absent from the public record. It is unclear whether the six dies ship as a single integrated module, as paired sets, or in another configuration. That decision directly affects total system cost and cooling requirements. A tightly integrated module simplifies board design but demands more aggressive thermal management; a looser coupling could ease heat constraints at the cost of higher latency between chips.
Volume figures remain unconfirmed as well. “Full production” describes a status, not a quantity. Without wafer-start data from TSMC or unit shipment numbers from Nvidia’s SEC filings, the actual scale of the ramp is not independently verifiable. The next concrete data points should arrive with Nvidia’s quarterly earnings report and TSMC’s own revenue disclosures, both of which will face pointed analyst questions about allocation and output.
The competitive landscape these chips enter
Nvidia’s six-chip platform does not arrive in a vacuum. AMD has been shipping its Instinct MI300X accelerators and has previewed the MI350 series built on a next-generation architecture. Google continues to expand deployment of its in-house TPU accelerators, most recently the Trillium (TPU v6) generation. Amazon has its Trainium chips, now in a second generation powering parts of AWS. And a wave of AI chip startups, from Cerebras to Groq, is pitching alternatives that promise better performance per watt or per dollar on specific workloads.
None of those competitors has yet matched Nvidia’s installed software ecosystem. CUDA, Nvidia’s parallel-computing platform, remains the default development environment for most AI researchers, and switching costs are high. That software moat gives Nvidia pricing power that pure hardware comparisons do not capture. Still, the competitive pressure is real: if the six-die platform’s specs or availability disappoint, customers now have more fallback options than at any point in the current AI hardware cycle.
Export controls add another variable
Any discussion of Nvidia’s next-generation hardware in 2025 and 2026 is incomplete without acknowledging U.S. export restrictions. The Bureau of Industry and Security has progressively tightened rules on which AI chips can be sold to China and other restricted destinations. Nvidia has already had to create different product variants to comply with earlier rounds of controls, and each new platform raises the question of whether its performance crosses thresholds that trigger additional licensing requirements.
For Nvidia, export controls create a two-track market: unrestricted customers (primarily in the U.S., Europe, Japan, and allied nations) who can buy the most powerful configurations, and restricted markets where different i SKUs or different i products must be offered. How much of the six-chip platform’s total addressable market falls into each track will shape revenue projections and could influence how aggressively TSMC allocates capacity to the program.
What to watch through mid-2026
The CES keynote set the starting line. The next milestones that will fill in the picture are specific and trackable:
- Nvidia’s quarterly earnings calls, where management will face questions about unit volumes, average selling prices, and gross margins for the new platform.
- TSMC’s revenue mix disclosures, which will reveal how much of the foundry’s advanced-node and advanced-packaging output is flowing to this program versus other customers.
- Cloud provider capital-expenditure updates from Microsoft, Google, Amazon, Meta, and Oracle, which will indicate whether procurement has shifted to the new chips or remains concentrated on prior-generation hardware.
- Official datasheets and technical briefs from Nvidia, expected to accompany product launches and GTC presentations, which will finally put hard numbers on memory, bandwidth, and power consumption.
Until those disclosures arrive, the confirmed facts are narrow but solid: six TSMC-fabricated chips, a multi-die architecture, full production status, and a direct public statement from Nvidia’s CEO tying the company’s near-term AI roadmap to this platform. For teams planning large-scale AI infrastructure, that is enough to start serious procurement conversations. It is not yet enough to sign long-term power and cooling contracts or lock in system-level designs. The gap between those two positions is exactly where the next few quarters of earnings reports and technical disclosures will land.
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*This article was researched with the help of AI, with human editors creating the final content.
