Most electronic components get worse as they shrink. Signals blur, heat climbs, and the line between a digital “one” and “zero” starts to dissolve. A research team at the Institute of Science Tokyo has built a memory device that does the opposite: at just 25 nanometers across, smaller than most viruses, it distinguishes its on and off states more sharply than any ferroelectric tunnel junction, or FTJ, reported before.
The device recorded a tunneling electroresistance (TER) ratio of 2,200, a measure of how cleanly it separates those two states. For context, many experimental FTJs at similar scales struggle to reach ratios in the low hundreds. A higher TER means the device wastes less energy deciding whether a bit is stored or erased, which translates directly into less heat generated per operation. Multiply that saving across the billions of memory cells packed into a modern chip, and the implications for smartphones, laptops, and data centers become significant.
The findings were published in the journal Nanoscale and confirmed by an institutional announcement from the Institute of Science Tokyo in early 2025.
Inside the 30-nanometer stack
The FTJ is built from three layers: a 5-nanometer platinum bottom electrode, a 20-nanometer ferroelectric film made of scandium-aluminum nitride (ScAlN), and a 5-nanometer platinum top electrode. The total thickness is 30 nanometers, roughly one-thousandth the width of a human hair.
What makes the result surprising is the ferroelectric layer’s behavior at small dimensions. In most ferroelectric materials, shrinking the film weakens the polarization that stores data, degrading performance. ScAlN appears to buck that trend. The researchers found that reducing the device’s lateral size actually sharpened the contrast between conductive and insulating states, producing the record TER ratio at the smallest geometry they tested.
Crucially, the fabrication process is compatible with existing CMOS manufacturing workflows. While ScAlN is not yet a staple of high-volume chip plants, the broader device architecture relies on deposition techniques already used in semiconductor fabs. That compatibility is what separates a laboratory curiosity from a technology with a plausible path to production, though significant engineering hurdles remain before any foundry could print billions of these junctions on a single wafer.
Why overheating matters now more than ever
Heat is the silent tax on every computation. Each time a memory cell switches, it dissipates energy as waste heat. In a phone, that heat throttles the processor and drains the battery. In a data center, it demands massive cooling systems that can account for 30 to 40 percent of a facility’s total electricity bill, according to estimates from the U.S. Department of Energy.
The problem is intensifying because demand for memory density keeps rising. Artificial intelligence workloads, high-resolution video, and always-on sensors all require more data to be stored closer to the processor, in denser arrays that generate more heat per square millimeter. Conventional flash memory and DRAM are approaching physical limits where further shrinking produces diminishing returns and escalating thermal costs.
An FTJ that improves as it shrinks would invert that equation. Instead of trading performance for density, engineers could pursue both simultaneously, building memory that runs cooler precisely because it is smaller. That is the promise embedded in the Science Tokyo results, though it has not yet been tested under the sustained, repetitive workloads that commercial memory must endure.
Parallel breakthroughs in heat-resistant memory
The Science Tokyo FTJ is not the only recent advance targeting the intersection of memory and heat. Two other research programs, working on different problems with different materials, have produced results that reinforce the broader trend.
At the University of Southern California, a team published results in the journal Science describing a memristor built from a stack of graphene, hafnium oxide, and tungsten that operates reliably at temperatures up to 700 degrees Celsius. The device maintained an on/off ratio greater than 1,000 and retained data for more than 50 hours at extreme heat. The key innovation was using graphene as a barrier layer to block electrode atom diffusion, the failure mechanism that destroys conventional memristors at high temperatures. Funding came from the National Science Foundation, the Air Force Office of Scientific Research, the Air Force Research Laboratory, and the Army Research Laboratory.
The USC device solves a different problem than the Science Tokyo FTJ. Consumer electronics rarely encounter 700-degree environments, but jet engines, deep-well drilling equipment, and spacecraft do. Placing memory and sensors directly in those extreme zones, without bulky cooling or shielding, could open applications that are currently impractical.
Meanwhile, researchers at Fudan University built a full-featured flash memory chip called ATOM2CHIP that bridges two-dimensional materials with conventional CMOS control logic. Published in Nature, the work demonstrated instruction operations, parallel operations, and random access with a reported cell yield of roughly 94.3 percent, switching speed of 20 nanoseconds, and energy consumption of 0.644 picojoules per bit. The chip represents one of the most complete system-level demonstrations of 2D-material memory to date, though its performance metrics come from the research team’s own measurements and have not yet been independently verified by a third-party laboratory.
What has not been proven yet
None of these three devices has been tested under the conditions that commercial memory must survive. For the Science Tokyo FTJ, no publicly available data shows how the device performs across millions or billions of read-write cycles, the kind of endurance testing that flash memory and DRAM undergo before qualification. The TER ratio of 2,200 was measured under controlled laboratory conditions, and sustained real-world workloads introduce stresses, from thermal cycling to voltage drift, that can degrade performance over time.
Scaling presents its own unknowns. Moving from a handful of devices on a research wafer to a commercial memory array containing billions of cells introduces failure modes that do not appear at small scale: line resistance, sneak currents between adjacent cells, and variability across large die areas. The ScAlN ferroelectric layer, while promising, is less established in high-volume manufacturing than materials like hafnium zirconium oxide, and foundries would need to validate that they can deposit it with the uniformity and throughput required for mass production.
No direct on-the-record comments from the Science Tokyo researchers address a timeline for commercial integration. The institutional announcement frames the work as a potential solution to overheating and battery drain, but that framing is aspirational. Translating a record TER ratio into measurable watts saved inside a running phone or server requires additional benchmarks that have not been disclosed as of June 2025.
The same caution applies to the Fudan ATOM2CHIP. Its 94.3 percent yield and sub-picojoule energy figures are encouraging for a prototype, but they were recorded under carefully chosen test conditions. Independent reproduction by another lab or a commercial foundry would substantially strengthen the case.
Three paths toward cooler, denser memory
These three research programs are complementary rather than competing. The Institute of Science Tokyo FTJ targets ultra-dense, low-power non-volatile memory for mainstream electronics. The USC memristor is designed to survive environments that would destroy conventional chips, enabling computing in aerospace and industrial settings. The Fudan ATOM2CHIP explores how atomically thin materials can extend scaling beyond the limits of traditional silicon-based memory.
Together, they suggest that the era of simply shrinking conventional memory cells is giving way to a more diverse landscape, one where new materials and device physics are enlisted to keep heat in check as data demands continue to accelerate. The physics behind each device is documented in peer-reviewed journals. The commercial future is not.
As more independent teams attempt to reproduce the FTJ’s TER ratio, stress-test the high-temperature memristor, and validate ATOM2CHIP’s endurance, the picture will sharpen. For now, the numbers in the primary literature deserve serious attention, but the boldest claims about transforming everyday electronics should be met with cautious optimism rather than certainty.
More from Morning Overview
*This article was researched with the help of AI, with human editors creating the final content.
