For the past two decades, most NASA spacecraft have relied on a processor called the RAD750, a radiation-hardened chip roughly as powerful as a late-1990s desktop computer. It has steered rovers on Mars, guided New Horizons past Pluto, and kept the James Webb Space Telescope running. But in February 2026, engineers at NASA’s Jet Propulsion Laboratory powered up something dramatically different: a next-generation space processor that, in early testing, is running roughly 500 times faster than the chips aboard any spacecraft flying today.
The chip, built under NASA’s High Performance Spaceflight Computing (HPSC) program, is not just a speed upgrade. It is designed to let spacecraft think for themselves, running artificial intelligence models onboard so they can dodge hazards, diagnose failures, and adjust scientific observations without waiting for instructions from Earth. If the performance holds through the grueling qualification process ahead, it could mark the biggest leap in spaceflight computing since the RAD750 first flew in 2005.
A processor built for decisions, not just data
The HPSC chip is a system-on-chip designed and manufactured by Microchip Technology Inc. under a $50 million firm-fixed-price contract with NASA. The agency selected Microchip after years of requirements development led by NASA’s Langley Research Center and JPL. Two variants exist: a fully radiation-hardened version engineered for the harshest deep-space environments, and a radiation-tolerant model suited for missions closer to Earth or inside shielded enclosures. Both share a common architecture, meaning mission teams can swap protection levels without rewriting their software.
That software layer is central to what makes the HPSC program different from a simple hardware refresh. NASA designed the chip to work with three established frameworks: the core Flight System (cFS), a reusable software platform that lets autonomy applications port across different hardware; AutoNGC, an autonomous navigation, guidance, and control package; and delay-tolerant networking (DTN), which manages data relay when communication links drop out. Together, these layers are intended to give a spacecraft the ability to detect a problem, calculate a response, and execute a maneuver on its own.
The practical need is sharpest beyond Mars. A radio signal from Jupiter takes upward of 30 minutes to reach Earth, and a round-trip command loop can stretch past an hour. Today’s onboard processors lack the horsepower to run complex AI models in real time, so spacecraft either wait for human commands or fall back on simple pre-programmed fault responses. A 500-fold jump in processing power would, in principle, let onboard software analyze sensor data, flag anomalies, and adjust course or instrument pointing within seconds.
What JPL testing has shown so far
According to a NASA technology update and a corresponding JPL news release, engineers at JPL are subjecting the HPSC processor to radiation bombardment, thermal cycling, and mechanical shock designed to simulate conditions beyond Earth’s magnetosphere. Early results indicate the chip is operating at approximately 500 times the performance of current radiation-hardened flight processors.
That number exceeds the program’s original target. When NASA awarded the Microchip contract, the HPSC program description set a floor of “over 100x” current spaceflight computing capability. Hitting five times that threshold in early lab work suggests the hardware is outperforming internal projections, though the gap between a lab indication and a flight-qualified rating remains significant.
JPL’s test campaign is not limited to raw speed benchmarks. Engineers are running representative workloads for navigation, hazard detection, and instrument control while simultaneously stressing the device with temperature swings and radiation bursts. The goal is to prove that the processor can maintain deterministic behavior and fault tolerance under realistic mission conditions, not just peak performance on a clean bench.
The long road from lab bench to launch pad
Strong early numbers do not guarantee the same performance in flight. Radiation-hardened processors must survive total ionizing dose accumulation, single-event upsets caused by cosmic rays, and thousands of thermal cycles. Characterizing all of that can take years. In past programs, engineers have sometimes had to derate clock speeds or limit power modes to maintain reliability, cutting into gains that looked impressive in the lab.
Power consumption is another open question. Higher performance typically means more heat and higher power draw, both tightly constrained on deep-space missions that depend on solar arrays or radioisotope thermoelectric generators. NASA has not yet released detailed power-performance curves or thermal design guidelines for HPSC-based avionics. Until those numbers are public, it is difficult to assess how much of the theoretical 500x gain will survive in a spacecraft with a strict power budget.
There is also no public timeline for which mission will carry the chip first. NASA’s documentation names cFS and AutoNGC as integration targets but does not specify whether a flagship planetary mission, a lunar lander, or a smaller technology demonstrator will be the debut platform. Candidates that could benefit from the upgrade include NASA’s Dragonfly rotorcraft mission to Saturn’s moon Titan, scheduled for the mid-2030s, and future elements of the Artemis lunar architecture, though no official selection has been announced.
Why independent validation matters
Every load-bearing claim about the HPSC chip currently traces back to NASA itself: the agency’s technology announcements, the program page, and Goddard Space Flight Center engineering documentation. That gives the core facts strong institutional credibility, but it also means the information has passed through NASA’s communications review process, which tends to spotlight positive milestones.
No independent laboratory, university research group, or defense agency has published a separate evaluation of the chip’s performance. In the space-processor field, independent validation typically arrives later, often after a chip flies on a demonstration mission or after NASA presents detailed technical papers at venues like the IEEE Aerospace Conference. Until that happens, the 500x figure should be understood as NASA’s own early assessment rather than a consensus finding confirmed by third-party testing.
The $50 million contract value, the selection of Microchip Technology, and the existence of two processor variants are all documented in official government procurement records and are not in dispute.
What a generational leap would mean for exploration
Even if the final qualified performance lands closer to the original 100x target than the 500x early indication, the upgrade would still represent the largest jump in spaceflight computing in at least two decades. Missions to the outer planets, the asteroid belt, and eventually interstellar space would gain the ability to run sophisticated onboard science analysis, compress development timelines for autonomous navigation, and shed the conservative fault-protection logic that keeps today’s spacecraft idle while they wait for a reply from Earth.
At the higher end of the performance range, the implications grow more dramatic. A spacecraft orbiting Europa could autonomously identify a plume eruption, repoint its instruments, and begin collecting data before a ground controller even learns the event occurred. A lunar lander could process terrain imagery and select a safe touchdown site in real time during descent, without relying on a pre-mapped landing ellipse chosen months earlier.
As of mid-2026, the HPSC chip remains on JPL’s test stands, working its way through the qualification gauntlet that every space-grade component must survive. The direction is clear: future missions will carry far more onboard intelligence than anything that has flown before. How much more, exactly, depends on what the chip looks like after years of radiation, thermal stress, and the unforgiving math of a spacecraft power budget.
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*This article was researched with the help of AI, with human editors creating the final content.
