At an IEEE conference in Shanghai in June 2025, Huawei introduced what it calls the “Tau Scaling Law,” a framework that positions three-dimensional chip stacking, not smaller transistors, as the primary engine of future computing gains. The proposal, distributed globally through a Dutch-language release on PR Newswire, argues that vertical silicon integration should succeed the flat-die shrinkage that has defined semiconductor progress for six decades.
If the idea catches on beyond Huawei’s walls, it could change how chipmakers, governments, and investors measure progress in an industry worth more than $600 billion a year.
The problem Tau is trying to solve
Moore’s Law, the observation Intel co-founder Gordon Moore articulated in 1965, held that transistor density on a chip roughly doubles every two years. For most of its history, the industry delivered on that prediction by printing ever-smaller transistors using increasingly advanced lithography. But the returns have been diminishing. At sub-3nm process nodes, where gate lengths no longer correspond neatly to the marketed node name, quantum tunneling effects, extreme heat density, and fabrication costs running into the tens of billions of dollars per fab have made each generational jump harder to justify.
Huawei’s Tau Scaling Law reframes the question. Instead of asking how small transistors can get on a single flat die, it asks how many active silicon layers can be stacked vertically and connected through dense, high-bandwidth interconnects. The concept treats layer count, interconnect pitch, and vertical power delivery as the new variables that define generational improvement.
The company has not yet published the underlying math. No formal paper or preprint has surfaced as of July 2025, and the PR Newswire release contains no quantitative performance projections, power-density benchmarks, or production timelines. That makes Tau, for now, more of a conceptual thesis than a testable prediction.
Why Huawei chose an IEEE stage
The venue was not accidental. IEEE conferences are where chip engineers publish refereed research and debate technical standards. Presenting Tau at an IEEE gathering signals that Huawei wants the idea evaluated as engineering, not marketing. But a critical distinction remains unresolved: IEEE events host everything from fully peer-reviewed papers to invited industry keynotes with no external vetting. The company has not clarified which format its presentation took, and IEEE conference organizers have not issued a public statement confirming the paper’s review status.
That gap matters. A refereed paper would mean independent experts examined the mathematical relationships behind Tau scaling. An invited keynote would carry no such endorsement. Until the presentation materials or a companion paper become publicly available, the technical community cannot verify the rigor behind the proposal.
The PR Newswire distribution, syndicated across multiple regional editions and accessible through PR Newswire’s media platform, ensures the announcement reached industry analysts and trade press worldwide. However, no corresponding post has appeared on Huawei’s own corporate website, and no named researchers have been attached to the formulation. Scientific scaling laws typically carry their authors’ names, which lets the community check prior publications, related patents, and earlier conference work.
Huawei is not alone in stacking chips
Three-dimensional chip integration is already an active field, and several of Huawei’s competitors have shipped commercial products built on vertical stacking architectures. TSMC’s SoIC (System on Integrated Chips) technology has been in volume production for select high-performance computing products since 2022, bonding multiple chiplets face-to-face with micron-scale interconnects. Intel’s Foveros packaging, which debuted in the Lakefield processor and expanded with Meteor Lake, stacks logic tiles vertically to blend high-performance and low-power cores. Samsung has pursued vertical NAND flash for years and has its own logic-stacking research programs.
The broader industry is also converging on chiplet interoperability through the Universal Chiplet Interconnect Express (UCIe) standard, backed by Intel, AMD, Arm, TSMC, Samsung, and others. UCIe aims to let chiplets from different vendors snap together in 2.5D and 3D configurations, much like USB standardized peripheral connections decades ago.
What Huawei’s Tau proposal appears to add is not a new stacking technique but a unifying mathematical framework, a single scaling law that could replace Moore’s Law as the industry’s shared yardstick. The PR Newswire release, however, does not explain how Tau’s framework differs from or improves upon the roadmaps already published by TSMC, Intel, or Samsung. Without that comparison, it is difficult to judge whether Huawei is proposing something genuinely novel or packaging an existing industry trajectory under a memorable name.
The export-control backdrop
Any discussion of Huawei’s semiconductor ambitions sits against the backdrop of U.S. export controls that have restricted the company’s access to advanced chipmaking equipment since 2020. Huawei’s primary manufacturing partner, Semiconductor Manufacturing International Corporation (SMIC), operates without access to ASML’s most advanced extreme ultraviolet (EUV) lithography systems, which are essential for producing chips at the leading edge of traditional 2D scaling.
That constraint gives Huawei a strategic incentive to champion a scaling paradigm that does not depend on EUV lithography. If the industry’s definition of progress shifts from nanometer-node shrinkage to vertical integration, Huawei’s inability to access the latest lithography tools becomes less of a competitive disadvantage. This does not invalidate the technical merits of 3D stacking, which are real and widely acknowledged, but it does add a geopolitical layer to the framing that readers should keep in mind.
What to watch for next
Two concrete signals will determine whether Tau gains traction beyond Huawei’s own communications.
The first is publication. A genuine scaling law should be falsifiable. Engineers need to see the mathematical relationship, its assumptions, boundary conditions, and example calculations so they can plug in parameters like layer count, interconnect pitch, and power density and check whether predicted performance matches real hardware. If Huawei releases a formal technical paper or preprint laying out that math, the proposal moves from thesis to testable claim.
The second is adoption. If third-party chipmakers, foundries, or research institutes begin referencing Tau in their own roadmaps, conference papers, or cross-company collaborations, that would suggest the concept has value as a shared language for 3D scaling. If it remains confined to Huawei’s press releases and investor decks, it will likely be remembered as a branding exercise.
A bid to redefine what progress looks like
Even without detailed equations, the strategic weight of Huawei’s framing is real. For decades, the semiconductor industry communicated progress in nanometer nodes and transistor counts. Investors, policymakers, and the public learned to treat those numbers as shorthand for technological leadership. A shift toward layer counts, stack heights, and 3D interconnect density would demand a different mental model entirely.
That shift could ripple outward. Research budgets might tilt toward advanced packaging, thermal interface materials, and power delivery networks designed for vertical architectures. Government subsidy programs, many of which still define “leading edge” by lithographic node, might need updated criteria that recognize gains achieved through stacking. Universities could expand curricula in heterogeneous integration and chiplet-based design.
For now, those downstream effects remain speculative. The established facts are narrow: Huawei has coined the Tau Scaling Law, chosen a prominent IEEE venue to introduce it, and built the concept around vertical chip stacking as the successor to Moore-style shrinkage. Whether Tau becomes the semiconductor industry’s next shared framework or a footnote in Huawei’s marketing history depends entirely on what comes next: the math, the hardware, and whether anyone outside Huawei decides to use it.
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*This article was researched with the help of AI, with human editors creating the final content.
