For decades, chipmakers kept Moore’s Law alive by shrinking transistors sideways, etching ever-finer features into flat slabs of silicon. That playbook is running out of room. Now a team at the University of Illinois Urbana-Champaign has demonstrated a different direction: up. Their results, published in Nature in June 2026, show silicon transistors stacked three layers high on a single chip, 625 devices per tier, with each layer delivering the same current density as transistors built the traditional way on a bulk-silicon wafer.
If the technique can be scaled from a lab demonstration to a factory floor, it would give the semiconductor industry a concrete new route to keep cramming more transistors onto a chip without relying on exotic materials or pushing lithography to even more punishing dimensions.
Why going vertical is so hard
The idea of stacking transistor layers is not new. Researchers have chased monolithic three-dimensional integration for years, and earlier demonstrations used carbon nanotubes or metal-oxide thin-film transistors to sidestep a brutal thermal problem: conventional silicon processing requires temperatures above 1,000 degrees Celsius, hot enough to melt the copper wiring already laid down on a finished chip layer beneath.
A landmark 2017 Nature paper from Stanford and MIT showed monolithic 3D integration using carbon-nanotube transistors paired with resistive RAM, proving the concept was physically possible. Other groups have pursued metal-oxide channels for the same goal. Both approaches kept temperatures low enough to protect underlying circuitry, but neither matched the raw electrical performance of silicon.
The Illinois team attacked the thermal barrier head-on. Their fabrication process stays at or below 400 degrees Celsius, a threshold known in the industry as compatible with back-end-of-line (BEOL) processing. That is cool enough to leave finished metal interconnects intact on the layers below, yet the resulting transistors are crystalline silicon, not a compromise material.
What the numbers actually show
Two metrics anchor the result. First, the stacked transistors produced current densities above 650 microamps per micrometer, putting them squarely in the performance range of devices fabricated on standard bulk-silicon wafers. Second, threshold-voltage maps covering all 625 devices on each of the three tiers showed uniform electrical behavior from top to bottom.
Uniformity matters as much as peak performance. A single fast transistor is a lab curiosity; hundreds of transistors behaving consistently across multiple stacked layers is evidence that a manufacturing process could, in principle, produce working circuits. The Illinois group went further, building inverters, ring oscillators, and small SRAM memory cells from the stacked devices. All three tiers participated in functioning logic, and the switching characteristics matched simulations based on bulk-silicon parameters. That rules out the possibility that the good numbers came from cherry-picked devices on a single lucky layer.
Taken together, the combination of silicon-grade drive current, three-tier uniformity across hundreds of devices, and working circuit demonstrations is what separates this result from prior monolithic 3D work. Earlier approaches traded performance for thermal compatibility. This one did not.
The gap between a demo and a product
A 625-transistor test array is a long way from the billions of transistors on a modern processor. The published data do not include yield or defect-density measurements across full 200-millimeter or 300-millimeter wafers, the standard formats used in commercial fabs. Without those numbers, no one can say how many good dies a foundry would pull from a production run.
Long-term reliability data are also missing. Chips in phones and servers endure years of thermal cycling, and electromigration (the slow drift of metal atoms under sustained current) can degrade interconnects over time. Neither the Nature paper nor the university’s institutional statements include accelerated-lifetime testing for the stacked structures. That gap is normal at this stage of research, but it means the path from proof of concept to qualified product remains long.
Thermal management raises its own questions. Each additional transistor layer adds heat sources and longer vertical wiring. The current work validates three tiers; commercial visions sometimes call for four, six, or more. Without thermal-profile and signal-integrity data beyond three layers, predicting how far the architecture can stretch before self-heating erodes its gains is guesswork.
Cost is perhaps the most consequential unknown. Today’s leading-edge chipmakers already offer 3D packaging: TSMC’s SoIC and Intel’s Foveros bond separately manufactured chiplets into dense stacks. Those methods are proven in production but rely on relatively coarse inter-die connections. Monolithic stacking promises far denser vertical wiring, but whether it saves money or adds cost at scale depends on yield, throughput, and the capital expense of retrofitting fabs for low-temperature crystalline-silicon deposition and precise layer-to-layer alignment. None of those figures appear in the current data.
Where this fits in the scaling race
The semiconductor industry has spent the last several years hedging its bets. TSMC, Samsung, and Intel are all investing in advanced packaging, backside power delivery, and new transistor architectures like gate-all-around nanosheets. Each of those efforts addresses a different bottleneck: interconnect density, power delivery, or electrostatic control. Monolithic 3D stacking attacks a complementary problem, the sheer number of transistors you can fit on a given area of silicon, by adding a vertical dimension to the logic itself rather than just the packaging.
What makes the Illinois result notable within that landscape is its insistence on staying within the silicon ecosystem. Carbon nanotubes and metal oxides may still find roles in specialized applications, but a process that uses the same channel material the entire industry already knows how to design around, simulate, and test has a lower adoption barrier. Foundries would not need to requalify an unfamiliar material; they would need to master a new deposition and alignment sequence for a familiar one.
That said, mastering that sequence at scale is itself a formidable challenge. The research opens a promising direction, not a finished roadmap. The device metrics and circuit demonstrations published in Nature justify serious attention from the industry, but the hardest questions (manufacturability at volume, long-term reliability, and cost competitiveness with existing 3D packaging) remain unanswered. Subsequent rounds of research, likely involving partnerships with foundries or equipment makers, will determine whether stacking silicon three layers deep in a lab can become stacking it reliably in a factory.
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*This article was researched with the help of AI, with human editors creating the final content.
