Building a superconducting qubit today requires depositing an insulating layer just a few atoms thick between two superconducting films. Get that layer slightly wrong and the qubit misbehaves or fails entirely. The step is one of the most delicate in quantum chip fabrication, and it has stubbornly resisted the kind of mass production that made classical silicon chips cheap and reliable.
A pair of researchers at Brookhaven National Laboratory think they have found a workaround. In a study published in Physical Review A, physicists Mingzhao Liu and Dylan Black of Brookhaven’s Center for Functional Nanomaterials modeled a transmon qubit that replaces the conventional superconductor-insulator-superconductor (SIS) Josephson tunnel junction with a superconductor-constriction-superconductor (ScS) nanobridge. Instead of sandwiching a fragile insulating barrier between two superconducting layers, the ScS design narrows a single superconducting film into a tiny bridge. That constriction can be patterned with the same lithographic tools already running in silicon semiconductor fabs.
If the simulated performance translates to real hardware, the design could eliminate one of the biggest yield-limiting steps standing between today’s modest quantum processors and the large-scale, fault-tolerant machines that fields like drug discovery, materials science, and cryptography are waiting for.
Why the junction matters
The Josephson junction is the heart of a transmon qubit. It creates the nonlinear energy levels that let engineers treat a superconducting circuit as a controllable two-state quantum system. In the standard SIS version, an oxide barrier only one or two nanometers thick separates two superconducting electrodes. Fabricating that barrier uniformly across an entire wafer is notoriously difficult. Contamination, thickness variation, and grain boundaries all degrade qubit coherence, the length of time a qubit holds quantum information before errors creep in.
Major quantum hardware programs at IBM, Google, and elsewhere have invested heavily in refining SIS junction fabrication, pushing coherence times from microseconds into the hundreds-of-microseconds range. But each new generation of processor demands more qubits packed more tightly, and the SIS barrier remains a persistent source of defects. A junction architecture that sidesteps the barrier altogether could, in principle, make qubit fabrication look more like conventional chipmaking.
What the Brookhaven study found
Liu and Black’s computational analysis shows that a coplanar ScS nanobridge can reproduce the anharmonicity and energy-level structure a transmon needs to function. Anharmonicity is what prevents a qubit’s control pulses from accidentally exciting higher energy states, and it is a non-negotiable requirement for reliable gate operations. Their model indicates the ScS design achieves this while avoiding the fabrication complexity of an ultra-thin oxide layer.
In a Brookhaven Lab statement, Liu said the constriction-junction approach “could enable easier production of quantum building blocks” without compromising the coherence and gate quality that make transmons useful. The work falls under the Co-design Center for Quantum Advantage (C2QA), a Department of Energy National Quantum Information Science Research Center headquartered at Brookhaven, whose mission centers on scalable, fault-tolerant quantum systems.
The modeling study builds on earlier experimental groundwork. Researchers have previously fabricated epitaxial CoSi2 thin-film SQUIDs with constriction-type junctions on silicon substrates, showing that at least one candidate superconducting material platform is physically viable. That gives the simulation a tangible starting point, even if no one has yet built a full transmon qubit from the material. The DOE’s Office of Scientific and Technical Information cataloged the final publication under report identifier BNL-225868-2024-JAAM, tying the work to Brookhaven and to federal funding through C2QA.
The gap between simulation and silicon
The most important caveat is straightforward: no physical ScS transmon qubit has been fabricated, cooled to the millikelvin temperatures superconducting qubits require, and measured for coherence time or gate fidelity. At least, no such result appears in any publicly available record tied to this team as of early 2026. Simulations can predict performance under idealized conditions, but real superconducting qubits contend with material defects, surface oxides, and stray electromagnetic fields that models may not fully capture.
The “silicon-compatible” label also carries fine print. Compatibility with existing fabrication lines depends on whether the chosen superconducting material can survive the thermal budgets, chemical environments, and integration steps of a working semiconductor process. The CoSi2 SQUID work is encouraging, but translating a SQUID demonstration into a qubit with competitive relaxation and dephasing times is a separate engineering challenge. Junction geometry, film uniformity, and packaging all influence how a device behaves once it is wired into a larger circuit.
Then there is the question of scale. No detailed roadmap with target qubit counts, integration densities, or timeline milestones has been published alongside the modeling work. Whether the ScS architecture can match or exceed the thousands-of-qubit targets that IBM’s Heron processors or Google’s Willow chip are pursuing with conventional SIS transmons is an open question only future experiments can answer.
Independent replication is also missing. The study originates from a single group at one national laboratory. Peer review in Physical Review A confirms the methodology met the journal’s standards, but confirmation from other labs, especially groups with different superconducting materials and fabrication tools, would strengthen the case considerably.
System-level unknowns
Even a qubit that performs well in isolation still has to coexist with control wiring, readout resonators, cryogenic packaging, and error-correcting codes. The ScS nanobridge changes the local electromagnetic environment of the junction region compared with an SIS barrier. That shift could interact in subtle ways with microwave control pulses or with neighboring qubits on a densely packed chip. Liu and Black’s paper focuses on single-qubit characteristics; multi-qubit crosstalk and layout constraints remain largely unexplored.
For context, the transition from a promising single-qubit design to a multi-qubit processor has historically taken years even for well-funded teams. Google’s path from its first transmon demonstrations to the 105-qubit Willow chip spanned roughly a decade of iterative engineering. A new junction architecture, however elegant on paper, would need to traverse a similar gauntlet of integration challenges.
What this means for the qubit scaling race
The practical takeaway is narrow but real. The ScS nanobridge eliminates the insulating tunnel barrier that makes SIS junctions difficult to fabricate reproducibly. If experimental groups can now build ScS transmons and show coherence times within striking distance of the best SIS devices, the door opens to leveraging mature silicon-processing infrastructure for quantum chips. That would not, by itself, solve the many other challenges of fault-tolerant quantum computing, from error correction overhead to cryogenic wiring density, but it could remove one of the most delicate and yield-limiting fabrication steps from the stack.
Until hardware results appear, the ScS transmon is best understood as a promising candidate architecture rather than a proven replacement for SIS junctions. The concept is grounded in established superconducting physics, the modeling has passed peer review, and related materials work demonstrates at least one silicon-compatible platform. But the metrics that matter most, coherence, gate fidelity, noise resilience, and large-scale integration, remain unmeasured in actual devices. The next phase will require coordinated work between materials scientists, device physicists, and fabrication engineers to find out whether the clean lines of a simulation survive contact with the inside of a dilution refrigerator.
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*This article was researched with the help of AI, with human editors creating the final content.
