A team of researchers has built a superconducting processor that integrates four dual-rail erasure qubits and used it to generate logical Bell and GHZ entangled states with reported high fidelities. The work, published in Nature Physics by Huang et al., represents one of the first demonstrations of multi-qubit logical entanglement in a dual-rail architecture, a design that converts the most common hardware errors into detectable “erasure” events rather than silent corruption. The result matters because scaling quantum computers depends on keeping error rates low enough for correction protocols to work, and erasure-biased errors are far easier to correct than random bit-flips or phase errors.
What the Processor Actually Did
The experiment centered on a four-qubit superconducting processor where each logical qubit was encoded across two cavity modes, a scheme known as dual-rail encoding. In this setup, a single microwave photon occupies one of two cavities, and the logical states correspond to which cavity holds the photon. The key advantage is that the dominant failure mode, photon loss, kicks the system out of the logical subspace entirely. That leakage can be caught by a quick, non-destructive check without disturbing the encoded information, effectively turning an unknown error into a known, flagged one.
Using this processor, the team generated logical Bell entangled states between pairs of qubits, as detailed in the Nature Physics report, and extended the technique to produce three-logical-qubit GHZ states. The experiment also implemented a calibrated logical CNOT gate, the standard two-qubit entangling operation required for universal quantum computation. Both the logical-state fidelities and the CNOT process metrics were quantified in the peer-reviewed study, while the accompanying preprint version provides additional detail on Bell- and GHZ-state performance along with expanded appendices on calibration and error analysis.
Crucially, the team did not just show that entanglement was possible; they showed that it could be generated and measured while continuously monitoring for erasures. Whenever an erasure event was detected, the corresponding run could be discarded or handled differently in software, allowing the researchers to focus on runs where the logical subspace remained intact. This conditional approach is a first step toward fault-tolerant protocols that adapt in real time to detected hardware faults.
Why Erasure Errors Change the Math
Most superconducting qubits suffer from errors that look random to the processor: a phase drifts, a bit flips, and the system has no immediate way to know which qubit went wrong or how. Quantum error correction codes can still fix these problems, but the overhead is steep. Correcting an unknown error requires many more physical qubits per logical qubit than correcting a known, located error, and it typically demands deep, noisy circuits to perform repeated syndrome measurements.
Dual-rail encoding reshapes this tradeoff. A foundational architecture study in PNAS proposed importing the dual-rail idea from optical quantum information into superconducting cavities, laying out how photon loss can be converted into a dominant, detectable erasure channel. By arranging the hardware and control so that amplitude damping kicks the system out of the logical subspace, the architecture turns the hardest errors to correct into the easiest to identify. This shift lowers the threshold for fault tolerance and reduces the number of physical qubits needed to protect a logical qubit.
Subsequent experiments confirmed these ideas in working devices. One group demonstrated erasure-aware logical readout for a single dual-rail cavity qubit, showing in erasure-sensitive measurements that state-preparation-and-measurement errors could be separated from erasure events and that photon loss dominated over residual phase and bit-flip errors during idle periods. Another independent team implemented erasure detection in a different hardware geometry, using a double-post cavity to show in cavity-based tests that the same basic principle works beyond a single device design. Together, these experiments established that erasure-biased behavior is a robust feature across superconducting cavity platforms.
Building Blocks Behind the Gate
Generating entanglement between dual-rail qubits requires precise control over how photons move between cavities. The enabling primitive is a beamsplitter interaction that coherently mixes two modes. Prior work used a parity-protected converter to demonstrate high-quality beamsplitting, with parametric interactions characterized for both gate fidelity and noise bias. This beamsplitter operation forms the basis for single-qubit rotations within the dual-rail subspace and underpins the two-qubit entangling gates deployed on the new processor.
Mid-circuit erasure checks are just as important as clean beamsplitters. Multi-step entangling protocols give errors many opportunities to accumulate, and catching them in real time is essential for any scalable error-corrected system. A technical study on mid-circuit monitoring for dual-rail cavity qubits quantified the missed-erasure rate and the extra erasure and Pauli errors introduced by each check. That work showed that erasure detection can be threaded through a circuit without overwhelming the error budget, provided each check is carefully engineered to be gentle on the logical subspace.
The new four-qubit processor builds directly on these ingredients. High-fidelity beamsplitter operations supply the coherent control needed for entangling gates, while mid-circuit checks ensure that photon loss is caught and labeled rather than silently degrading logical states. The combination allows researchers to run sequences of gates long enough to generate Bell and GHZ states while still keeping track of when and where the hardware misbehaves.
A Growing Hardware Ecosystem
The dual-rail erasure concept is not confined to cavity-based devices. Other superconducting platforms have begun to adopt similar strategies, encoding information across multiple modes or elements so that loss events become detectable. Demonstrations with tunable transmons, for example, have shown that long coherence times and mid-circuit erasure detection can coexist in a circuit-based architecture, suggesting that the basic idea of erasure bias can be transplanted across different families of superconducting qubits.
Recent work has also pushed toward deliberately biased-erasure regimes, where hardware is tuned so that most imperfections manifest as detectable events and only a small residue remains as undetectable noise. Experiments with cavity qubits have reported hardware-efficient schemes that convert leakage into erasures and quantify logical assignment errors under these conditions. This direction points toward a future in which small error-correcting codes, tailored to an erasure-dominated noise model, can deliver meaningful logical performance without the massive overhead often cited for generic fault tolerance.
What This Means for Practical Quantum Machines
Much of the current discussion about quantum computing focuses on raw qubit counts and headline-grabbing demonstrations of algorithmic speedups. The dual-rail erasure processor highlights a different, arguably more important dimension: the structure of the underlying noise. By engineering a system where the dominant error is not only reduced but also labeled, the researchers have moved closer to hardware that can support efficient, scalable error correction.
In practical terms, erasure-biased architectures could significantly cut the resource cost of building useful quantum machines. Codes designed for erasures can tolerate higher physical error rates and require fewer physical qubits per logical qubit than codes optimized for arbitrary noise. Logical Bell and GHZ states, as demonstrated on the four-qubit processor, are the basic ingredients for more complex protocols such as teleportation, entanglement distillation, and lattice-surgery operations in topological codes. Showing that these states can be prepared with high fidelity in an erasure-aware setting is an early sign that the architecture can support more advanced fault-tolerant primitives.
There are still substantial challenges ahead. Scaling from four logical qubits to the hundreds or thousands needed for large-scale algorithms will require integrating more cavities or transmons without sacrificing coherence or control. Mid-circuit checks must remain low-error as circuits deepen, and the classical control stack must be able to react to erasure information on the fly. Moreover, the remaining non-erasure errors (those that do not kick the system out of the logical subspace) must be pushed low enough that modest-sized codes can handle them.
Even so, the trajectory is clear. With theory work outlining how dual-rail architectures can reshape fault-tolerance thresholds, single-qubit experiments validating erasure detection in multiple geometries, and now a four-qubit processor generating logical entanglement under active monitoring, the field is moving from conceptual promise to system-level demonstrations. If future devices can extend these techniques to larger logical registers while preserving an erasure-dominated noise profile, erasure-biased superconducting processors may become a leading contender for building practical, error-corrected quantum computers.
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*This article was researched with the help of AI, with human editors creating the final content.
