A team led by the Shenzhen International Quantum Academy reports demonstrating logical operations on a silicon-based quantum processor for the first time, a result that separates encoded, error-protected computation from the raw physical-gate experiments that came before it. The work uses a phosphorus donor cluster in silicon to implement the [[4,2,2]] error-detecting code, encoding two logical qubits and reporting fault-tolerant logical state preparation. For the quantum computing field, which has long debated whether silicon can compete with superconducting and ion-trap platforms, this is the clearest evidence yet that the material at the heart of classical chip manufacturing can also support the error-correction layer that practical quantum machines will require.
What is verified so far
The central result, described in a peer-reviewed report in Nature Nanotechnology, is presented by the authors as the first realization of logical operations in silicon. The IQASZ-led team built a logical quantum processor around a phosphorus donor cluster and implemented the [[4,2,2]] code, a small but meaningful error-detecting scheme that encodes two logical qubits from physical ones. Fault-tolerant logical state preparation was documented in the same paper, meaning the encoded states were created in a way designed to prevent certain classes of errors from spreading through the system and corrupting multiple qubits at once.
This result did not appear in isolation. An earlier study by the same group, published in Nature Electronics, established key prerequisites. That work demonstrated stabilizer-based quantum error detection in a donor-based silicon processor built from four nuclear spin qubits plus one electron auxiliary. The team reported a GHZ state fidelity of 88.5 plus or minus 2.3%, a metric that reflects how well the processor can prepare entangled states needed for error-detection protocols. Stabilizer measurements, the diagnostic backbone of most quantum error-correcting codes, were shown to work reliably in this architecture before the team attempted full logical operations.
The processor itself was fabricated using scanning tunneling microscopy, or STM, a technique that places individual phosphorus atoms into a silicon crystal with atomic precision. In an institutional announcement, IQASZ describes the achievement as the first full-stack logical operations on a silicon-based quantum processor, a framing that distinguishes it from earlier demonstrations of universal physical gates in silicon. Here, “full-stack” refers to the integration of device fabrication, qubit control, error detection, and logical-level operations within a single experimental platform.
That distinction matters. A 2019 preprint on quantum dots in silicon showed that universal logic at the physical-gate level already existed, operating above 1 kelvin and demonstrating that silicon spin qubits could, in principle, support arbitrary single- and two-qubit operations. What changed in 2026 is the jump from physical-level universality to logical-level operations, where operations act on encoded qubits rather than bare physical ones. The difference is roughly analogous to the gap between toggling individual transistors and running software on a chip: both involve the same underlying hardware, but the latter requires an abstraction layer that manages errors and complexity through coding and fault-tolerant protocols.
Access to the detailed methodologies and data in the Nature Nanotechnology article may require authentication through the Nature login portal, but the core claim is explicitly that logical qubits in silicon have been initialized, manipulated, and measured using an error-detecting code. For specialists, this marks the transition of donor-based silicon devices from proof-of-principle qubits to elements of a small, but structurally complete, logical processor.
The earlier Nature Electronics work can likewise be explored in more depth via the publisher’s access gateway, which underscores how central stabilizer measurements and entangled-state fidelities were to the subsequent logical demonstration. In sequence, the two papers show a progression from reliable syndrome extraction to complete encoded operations, all within the same donor-based silicon platform.
What remains uncertain
Several questions remain open despite the peer-reviewed confirmation of the core result. The available reporting does not include long-term coherence data for the [[4,2,2]] implementation. Coherence time, the window during which qubits retain useful quantum information, is one of the most important practical metrics for any quantum processor. Without published figures on how long the logical qubits stay coherent under repeated operations, it is difficult to assess how close this system is to running algorithms of meaningful depth or to implementing more powerful error-correcting codes that require many sequential gates.
Full error-rate breakdowns for the logical operations are also absent from the publicly available abstracts. While the earlier Nature Electronics paper reported the 88.5% GHZ fidelity figure, that number describes a precursor experiment, not the logical gate performance itself. Whether the logical operations improve on physical error rates, a condition sometimes called “below break-even,” has not been confirmed or denied in the sources reviewed here. Without that comparison, it is not yet possible to say whether encoding in this architecture currently offers a net advantage over operating directly on physical qubits.
Scalability projections are similarly missing. Silicon’s main selling point has always been its compatibility with existing semiconductor manufacturing, specifically CMOS fabrication lines that produce billions of classical transistors per chip. Yet the STM nanofabrication technique used in this experiment is a laboratory method, not a factory process. No institutional forecast or timeline for integrating this architecture into standard chip production has been published alongside the result, and there is no clear indication of how donor placement by STM might translate into large-scale, repeatable fabrication at industrial yields.
Earlier foundational work showed that silicon spin qubits can function at approximately 1.5 kelvin, a temperature far warmer than the millikelvin range required by many superconducting qubits. This thermal headroom could, in principle, ease cooling requirements and enable denser integration of control electronics near the qubits. However, the new logical-operations experiment does not yet map that thermal advantage onto a concrete scaling roadmap. Questions remain about cross-talk, wiring density, and whether donor-based devices can be multiplexed in large arrays without sacrificing coherence or gate fidelity.
Access to the detailed experimental conditions of the 1.5-kelvin work similarly runs through a publisher authentication page, and the available summaries do not explicitly connect those conditions to the donor-cluster devices used for logical encoding. As a result, any assumptions about operating temperature, cooling infrastructure, or integration with classical control electronics for the new processor would go beyond the evidence currently in hand.
Direct comparisons to competing platforms are also absent from the peer-reviewed record. Superconducting processors from companies such as Google and IBM, and trapped-ion systems from firms like Quantinuum, have each demonstrated forms of error correction and logical operations on their respective architectures. No benchmarking study places the silicon result alongside those efforts using common metrics such as logical error rates per gate, code distances, or circuit depth. Until such cross-platform benchmarks are available, claims about relative performance, speed, or scalability should be treated with caution and regarded as speculative rather than evidence-based.
How to read the evidence
The strongest evidence here comes from two peer-reviewed papers in Nature-family journals, both produced by the same IQASZ-led research group. The Nature Nanotechnology paper carries the headline claim directly: logical operations in silicon, implemented for the first time on encoded qubits using an error-detecting code. The Nature Electronics paper supplies the supporting technical foundation, particularly the stabilizer measurement procedures and entangled-state fidelity data that validate the underlying control and readout mechanisms. Together, these two publications form a coherent, internally consistent evidence chain from error detection to logical operation.
The institutional release from IQASZ adds context, particularly around fabrication methods and the “full-stack” framing, but it is a press communication rather than a peer-reviewed document. Its claims align with the journal papers, so there is no conflict, but readers should weight the journal results more heavily when assessing technical specifics such as fidelities, coherence behavior, or gate sequences. The release does not contain performance data beyond what the papers provide, and it does not attempt to quantify scalability, cost, or timelines for commercialization.
The older references, including the 2020 Nature work on operation near 1.5 kelvin and the 2019 preprint on universal physical gates in silicon quantum dots, serve as historical context rather than direct evidence for the 2026 result. They establish that silicon qubits were already functional and that physical-level universality was already demonstrated, which frames the new experiment as a step up the abstraction ladder rather than a first appearance of working silicon qubits. Taken together, the literature supports a cautious but clear conclusion: donor-based silicon devices have progressed from isolated qubits to small logical processors, yet key metrics on coherence, logical error rates, and manufacturability remain to be demonstrated before silicon’s long-promised advantage in quantum computing can be fully assessed.
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*This article was researched with the help of AI, with human editors creating the final content.
