Three separate research teams have reported techniques that directly attack one of the hardest problems in shrinking transistors and wiring below 10 nanometers: the sharp rise in electrical resistance at the point where metal contacts meet ultra-thin semiconductor channels. Their combined findings, spanning carbon nanotube transistors, two-dimensional molybdenum disulfide devices, and nanoscale metal interconnects, suggest that the contact-resistance bottleneck long predicted to stall chip scaling may be more solvable than the industry assumed.
Why Contact Resistance Stalls Smaller Chips
As transistor dimensions shrink, the area where a metal electrode touches a semiconductor channel gets smaller too. That shrinking contact zone forces current through an ever-tighter aperture, and resistance climbs steeply. The effect is not a minor nuisance. At scales below roughly 20 nanometers, contact resistance can dominate total device resistance, wiping out the speed and efficiency gains that smaller geometries are supposed to deliver.
A related constraint, sometimes called Boltzmann tyranny, limits how sharply a transistor can switch between its on and off states, which in turn forces designers to keep supply voltages higher than they would like. Together, these two barriers mean that simply making transistors smaller no longer automatically yields faster, cooler-running chips. Fixing contact resistance is therefore not an academic exercise; it determines whether the next several nodes of semiconductor scaling deliver real performance returns to data centers, phones, and AI accelerators.
Researchers are increasingly turning to alternative channel materials, new contact geometries, and exotic metals to overcome this impasse. The latest work on carbon nanotubes, monolayer semiconductors, and anisotropic interconnects points toward a future in which resistance at the smallest dimensions is engineered, not merely tolerated.
Carbon Nanotube Transistors Push Contacts to 18 Nanometers
A study published in Nano Letters tackled the problem head-on in carbon nanotube field-effect transistors, scaling contact lengths down to 18 nanometers in both PMOS and NMOS devices. In these ultra-scaled nanotube transistors, the researchers measured a clear reduction in leakage current, a metric called Imin that represents the residual current flowing when a transistor is supposed to be off. Leakage is a major contributor to wasted power in dense circuits, so lowering it has direct consequences for chip energy budgets.
The key mechanism was selecting carbon nanotubes with larger bandgaps. A wider bandgap raises the energy barrier that electrons must overcome to leak through the device in its off state, and the experimental data confirmed that Imin dropped significantly with these wider-gap CNTs. That finding matters because it shows a practical design knob, not just a theoretical one, that engineers can turn when building carbon nanotube logic at aggressive dimensions.
Most prior work on CNT transistors had focused on channel mobility and on-current, often assuming that contact regions would become a limiting factor long before the channel itself. Demonstrating that contact-region leakage can be tamed at 18 nanometers removes one of the louder objections to using carbon nanotubes as a silicon replacement. It also suggests that careful control over nanotube diameter and chirality (both of which determine bandgap) will be just as important as lithographic precision in future CNT-based logic.
The authors benchmarked their devices against state-of-the-art silicon transistors and found that, at comparable gate lengths, the carbon nanotube devices could achieve competitive switching characteristics with substantially lower leakage. That comparison is still early-stage: manufacturing uniform CNT arrays at wafer scale remains unsolved, and integrating them into existing process flows will be a major challenge. But the work shows that, at least from a contact-resistance standpoint, carbon nanotubes are not inherently disqualified at sub-20-nanometer nodes.
Equally important, the study’s methodology—systematically varying nanotube bandgap while holding other device parameters as constant as possible—offers a template for future research on alternative channel materials. Rather than treating contact resistance as an uncontrollable parasitic, it becomes a quantity that can be co-optimized with channel design, dielectric choice, and gate architecture.
Simulations Map Tunneling Limits in 2D Semiconductors
A separate computational study addressed the same bottleneck in a different material system: monolayer molybdenum disulfide, one of the most studied two-dimensional semiconductors. Using ab initio transfer-length-method simulations, the researchers modeled how current tunnels across the interface between a metal electrode and a single-layer MoS₂ channel for four representative metals: scandium, silver, gold, and palladium.
The simulations compared two contact geometries. In a top contact, the metal sits on the flat surface of the MoS₂ sheet. In an edge contact, the metal bonds to the exposed atomic edge of the sheet. The study found a universal transition in resistance scaling that depends on contact length, and it showed that edge contacts can substantially cut tunneling resistance relative to top contacts for certain metal choices.
That result is significant because most fabrication processes today default to top-contact layouts, which are easier to manufacture but may leave performance on the table. Identifying the crossover point where edge contacts become superior gives device designers a quantitative target for when the extra fabrication complexity pays off. It also clarifies which metals are likely to yield the lowest specific contact resistances when paired with monolayer channels, an important guide for experimentalists planning future process-development runs.
The work was hosted on arXiv’s technical platform, a preprint repository operated by Cornell-linked organizers, and has not yet undergone formal peer review. That caveat is standard for computational studies posted as preprints, but the specific metals and geometries tested align with experimental trends reported by other groups, lending the conclusions additional weight. As fabrication techniques for two-dimensional materials mature, the simulation framework could be used to screen new metal–semiconductor combinations before they ever reach the cleanroom.
Anisotropic Metals Could Outperform Copper Wiring
Even if transistors themselves improve, the tiny metal wires connecting them, called interconnects, face their own scaling wall. Copper, the industry standard since the late 1990s, suffers a sharp resistivity penalty as wire cross-sections drop below a few nanometers. Electrons scatter off wire surfaces far more frequently at those dimensions, and the added resistance slows signals and wastes power.
A peer-reviewed study in Physical Review Materials proposed a fix rooted in the shape of a metal’s Fermi surface, the abstract boundary in momentum space that describes how electrons move through a crystal. Metals whose Fermi surfaces are strongly anisotropic, meaning electrons travel much faster in some crystal directions than others, can be oriented so that the dominant electron velocities run parallel to the wire axis. That alignment reduces surface scattering at nanoscale dimensions, and the study predicted that properly chosen anisotropic metals could beat copper’s resistivity scaling penalty at wire widths of just a few nanometers.
If confirmed in fabrication, this approach would let chipmakers keep shrinking interconnect pitch without the exponential resistance cost that copper imposes. It could also open the door to application-specific wiring stacks in which logic, memory, and analog blocks each use different interconnect metals optimized for their particular current densities and delay budgets.
Practical implementation will not be trivial. Anisotropic metals often require tight control over crystal orientation, which may conflict with existing damascene processes. Reliability under high current densities and thermal cycling must also be validated. Nonetheless, the work reframes interconnect scaling as a materials-selection problem rather than a hard physical limit, much as high-k dielectrics and metal gates did for transistor scaling a decade ago.
A Narrower Path Forward for Scaling
Taken together, these three lines of research suggest that contact resistance and nanoscale wiring are not insurmountable barriers but demanding engineering problems with multiple, complementary solutions. Carbon nanotube transistors show that contact regions can be pushed to 18 nanometers while actually reducing leakage. Monolayer MoS₂ simulations map out when and how to use edge contacts and which metals to pair with them. Anisotropic interconnect metals offer a way to keep resistance in check even as wire widths approach just a few atoms across.
The common thread is precision: in material choice, device geometry, and crystal orientation. Instead of relying on brute-force lithographic scaling, future chip generations will likely depend on this kind of fine-grained co-design of channels, contacts, and interconnects. Large shared databases such as the NCBI-hosted archives for scientific literature and data are helping accelerate that process by making detailed results broadly accessible across disciplines.
None of these approaches is ready for immediate deployment in high-volume manufacturing. Carbon nanotube integration, 2D-material processing, and anisotropic-metal deposition all face substantial yield, cost, and reliability hurdles. Yet the trajectory of the research points away from a hard stop in scaling and toward a narrower but still navigable path. If industry and academia can translate these laboratory advances into robust process modules, the long-feared contact-resistance wall may turn out to be less a dead end than a sharp bend in the road for Moore’s Law.
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*This article was researched with the help of AI, with human editors creating the final content.
