Researchers at Argonne National Laboratory and SLAC have designed a detector chip that compresses X-ray data by factors of 100 to 250 in real time, directly on the silicon that captures each frame. The chip targets a specific bottleneck: next-generation X-ray and electron imaging facilities now fire millions of frames per second, producing data streams that overwhelm even the fastest storage and networking hardware. By shrinking that torrent at the source, the new architecture could let scientists extract results from experiments that would otherwise bury them in unprocessable information.
How the Chip Squeezes Data at MHz Speeds
The core design is detailed in a preprint on a 28-nanometer ASIC for on-chip data compression in MHz frame rate detectors. The paper describes a streaming, fixed-length lossy compression scheme implemented as a vector multiply-accumulate operation directly inside each detector pixel’s readout circuit. Fabricated on a 28 nm process node, the application-specific integrated circuit (ASIC) achieves analyzed compression ratios ranging from 100 to 250, meaning a single raw frame can be reduced to as little as 0.4% of its original size before it ever leaves the chip.
That approach differs from conventional pipelines, where raw frames travel off-detector through high-speed serial links to field-programmable gate arrays or GPUs sitting downstream. A peer-reviewed review in Frontiers in Physics explains how traditional architectures run into hard limits: data bottlenecks form at chip transceivers on the detector periphery and again at module-level bandwidth caps, forcing compromises between frame rate, detector area, and data fidelity. Pushing compression onto the detector itself eliminates both chokepoints at once by reducing the number of bits that ever touch those interfaces.
Because the compression is fixed-length and streaming, the chip can process each pixel’s signal on the fly as it is read out, without needing large intermediate buffers. The multiply-accumulate engine effectively projects the high-dimensional pixel data into a lower-dimensional representation that still preserves the features scientists care about. This hardware-efficient formulation is critical for running at MHz frame rates, where even nanoseconds of additional latency per pixel can add up to missed pulses.
Training the Silicon to Know What Matters
The lossy compression works because not every photon count in every pixel carries equal scientific value. The weights baked into the ASIC are trained on representative datasets, such as X-ray ptychography patterns and time-resolved diffraction images, and then hard-coded into the chip. An Argonne laboratory release describes the concept this way: the chips can be trained on what is most important for a given experiment, so they can compress and reduce data on the fly without sacrificing the information content that actually drives scientific conclusions.
An earlier preprint from 2022 laid groundwork for this strategy by describing a configurable digital architecture with selectable lossy and lossless compression blocks. That design was evaluated using both simulated and experimental X-ray ptychography datasets, and it aimed at pushing pixel-detector frame rates toward continuous operation near 1 MHz. The newer 28 nm chip builds on those results, scaling the compression ratio far higher while keeping the scheme simple enough to run inside each pixel at full frame rate.
Training-based compression raises questions about generality: will a chip optimized for one type of experiment perform well on another? The authors address this by focusing on classes of measurements, such as coherent diffraction imaging, where the salient features share common structure across samples. In principle, different ASIC variants could be tuned for other modalities. Over time, facilities may deploy families of trained detectors, each aligned with a particular experimental program.
Why Facilities Need On-Chip Compression Now
The urgency comes from a generation of light sources that have dramatically outpaced their data infrastructure. SLAC’s Linac Coherent Light Source, upgraded to LCLS-II, now delivers X-ray beams that can probe samples at repetition rates producing terabytes of raw detector output per second. LCLS-II was designed to produce X-ray pulses that are on average thousands of times brighter than those of its predecessor, enabling studies that track the motions of individual atoms and follow ultrafast chemical reactions in real time. Brighter pulses and faster repetition rates mean exponentially more data per experiment.
Without on-chip reduction, the data pipeline becomes the experiment’s speed limit. Storage arrays fill up, network links saturate, and scientists must either slow their measurements or throw away frames they cannot record. A 200-fold compression ratio applied at the detector turns an unmanageable flood into a stream that existing downstream hardware can handle, preserving the scientific throughput that these billion-dollar facilities were built to deliver. It also simplifies data management: experiments that once demanded petascale storage for raw frames can instead archive compressed representations and reconstruct key observables later.
The pressure is not limited to X-ray lasers. Electron microscopes and synchrotron beamlines are also pushing toward continuous MHz-rate imaging, and their detectors face similar constraints. A study of high-speed electron microscopy highlighted how detector and data-system limits can cap the effective time resolution of instruments, even when the beam itself could support faster measurements. Embedding compression at the sensor level offers a way to unlock that latent performance without completely overhauling facility-scale infrastructure.
Competing Approaches to Detector-Level Compression
The Argonne-SLAC ASIC is not the only effort to move computation closer to the sensor. A reconfigurable perovskite X-ray detector described in Nature Communications demonstrated in-detector convolution-kernel processing that enabled edge extraction and roughly 50% data reduction. That “compute-in-detector” concept operates at the material level rather than in digital readout logic, and its compression ratio is modest compared with the 100-to-250 range of the new ASIC. Still, it shows that the field is converging on the same principle: shrink data before it leaves the sensor plane.
A separate systems-level paper in Nuclear Instruments and Methods in Physics Research Section A tackled edge compression for billion-pixel X-ray cameras, placing the reduction step in near-detector electronics rather than on each pixel itself. That strategy suits very large-area detectors where per-pixel logic would be prohibitively complex or power-hungry. By contrast, the Argonne-SLAC design trades some silicon area inside each pixel for the ability to cut data volumes by two orders of magnitude at the earliest possible point.
These approaches may ultimately prove complementary. Material-level processing could perform simple feature extraction or thresholding before analog-to-digital conversion, digital ASICs could apply trained projections for aggressive lossy compression, and edge electronics could handle additional filtering or error correction. The optimal mix will depend on the scientific questions, acceptable information loss, and power and cooling budgets at each facility.
Building on a Growing Data Ecosystem
The compression ASIC does not exist in isolation; it is part of a broader ecosystem of tools and institutions responding to the data deluge from modern instruments. Preprints describing this work are shared through platforms like arXiv’s member-supported service (which has become a central channel for rapid dissemination in physics and engineering). That early visibility helps detector developers coordinate with beamline scientists, data scientists, and computing specialists long before hardware is deployed.
On the software side, facilities are investing in real-time analysis pipelines that can ingest compressed data streams and provide immediate feedback to users. The success of on-chip compression will depend not only on hardware but also on reconstruction algorithms, calibration procedures, and user interfaces that make compressed representations as scientifically transparent as possible. If those pieces align, future experiments may feel less like batch data collection and more like interactive exploration, with detectors and analysis systems acting together as a tightly coupled instrument.
For now, the Argonne-SLAC chip offers a concrete path past a looming barrier. By embedding trained, hardware-efficient compression directly into each pixel, it promises to turn overwhelming torrents of X-ray and electron data into manageable streams, allowing the next generation of light sources and microscopes to operate closer to their full potential.
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*This article was researched with the help of AI, with human editors creating the final content.
