Researchers have built working transistors from graphene nanoribbons less than a nanometer wide, achieving room-temperature switching performance that silicon struggles to match at similar scales. The devices, which use channels roughly 20 nanometers long and just 0.95 nanometers across, recorded on/off current ratios near 100,000, a threshold that makes them viable candidates for logic circuits in future chip designs. Paired with parallel advances in vertical transistors and ultrafast optical switches, these results point toward a generation of processors that could consume far less power than today’s silicon-based chips.
Sub-Nanometer Ribbons That Act Like Real Transistors
The central challenge in shrinking transistors beyond current limits is not just making them smaller but keeping them functional. Silicon loses its ability to block current reliably below about 5 nanometers, a problem known as short-channel effects. Graphene nanoribbons offer a workaround: by cutting graphene into strips just a few atoms wide, researchers can open an electronic bandgap in what is otherwise a zero-gap material, turning it into a semiconductor.
A team demonstrated this by fabricating field-effect transistors with 9-atom-wide nanoribbons measuring approximately 0.95 nm across. These devices operated at room temperature with on-state current exceeding 1 microamp at a drain voltage of negative 1 volt and an on/off ratio of roughly 10^5. The channel length sat at about 20 nm, well within the regime where silicon transistors begin to leak current uncontrollably.
What separates these results from earlier graphene experiments is the precision of the ribbon edges. The nanoribbons were built atom by atom using bottom-up chemical synthesis rather than carved from larger sheets, which tends to produce ragged edges that degrade performance. A detailed fabrication study of 9- and 13-atom-wide ribbons confirmed the process steps that yielded reproducible switching behavior, from precursor design to on-surface polymerization and cyclodehydrogenation. That level of atomic control is what finally allowed graphene to function as a true transistor channel rather than just a laboratory curiosity.
At the same time, these chemically grown ribbons highlight a trade-off between perfection and practicality. Bottom-up synthesis can deliver nearly ideal edges and predictable bandgaps, but aligning and contacting countless individual ribbons across a full wafer remains unsolved. The current devices prove that sub-nanometer channels can switch cleanly at room temperature; the next step is to translate that precision into a manufacturable architecture.
Vertical Architectures Push Below 5 Nanometers
Graphene’s role in next-generation chips extends beyond serving as the channel material itself. A separate line of research has shown that graphene electrodes can enable transistor geometries impossible with conventional metals. Using van der Waals stacking, which layers two-dimensional materials without the lattice-matching constraints of epitaxy, researchers have built vertical field-effect transistors with channel lengths near 4 nm while delivering on-current densities above 800 A/cm2 and on/off ratios reaching 2 × 105.
These vertical devices solve a different piece of the power puzzle. By orienting the current path perpendicular to the chip surface, they pack more transistors into the same footprint without widening the die. The graphene electrodes, just one atom thick, minimize parasitic capacitance that wastes energy every time a transistor switches state. For chip architects trying to keep power budgets flat while adding billions more transistors per generation, that combination of density and efficiency matters more than raw speed.
The tension between these two approaches, graphene-channel ribbons versus graphene-electrode vertical stacks, is itself instructive. Neither has yet demonstrated the billions-of-devices integration that commercial logic chips require. But they attack the power problem from complementary angles: one replaces the channel material, the other reimagines the device geometry. A future chip might use both, with ultra-short vertical paths for dense logic and narrow ribbons where extreme gate control is essential.
Optical Switching at Femtosecond Speeds
Power consumption in modern data centers is not limited to logic transistors. Interconnects, the links that shuttle data between cores, memory, and off-chip networks, account for a growing share of total energy use. Graphene-based photonic switches could address that bottleneck directly. Researchers demonstrated all-optical modulation in graphene-loaded plasmonic waveguides with a cross-section of just 30 × 20 nm2, a switching energy of approximately 35 femtojoules, and a switching time near 260 femtoseconds.
To put those numbers in context, 35 femtojoules is orders of magnitude less energy than a typical electrical transistor switching event in a modern processor. The 260-femtosecond response time is fast enough to handle terabit-per-second data rates without the electronic bottlenecks that currently force optical signals to be converted to electrical ones and back again at chip boundaries. A separate access-controlled link to the same work underscores the challenge of disseminating such optical results widely beyond paywalled journals (even as they become central to computing roadmaps).
If these plasmonic switches can be integrated alongside electronic transistors on the same substrate, they could eliminate one of the most wasteful steps in high-performance computing: the repeated optical-to-electrical conversion that burns power at every interface. In that scenario, graphene would not just make better transistors; it would help merge photonics and electronics into a single, tightly coupled platform.
Fabrication Hurdles and the Path to Mass Production
The gap between a working lab device and a commercial chip remains wide. Bottom-up synthesis of atomically precise nanoribbons produces excellent transistors one at a time, but no group has yet demonstrated wafer-scale placement of billions of aligned ribbons. Top-down methods, which etch graphene from the edges to narrow it below 5 nm, have shown room-temperature transistors with on/off ratios around 10,000 for the resulting nanoribbons. That is an order of magnitude lower than the bottom-up devices, reflecting the rougher edge quality that comes with etching. Still, etching is far more compatible with existing semiconductor manufacturing tools, making it the more likely near-term route to scale.
A separate effort has tackled the mechanical side of the problem. Researchers have demonstrated large-scale graphene NEM contacts with ultra-low pull-in voltages and narrow hysteresis windows, suggesting that mechanical switching elements based on graphene can be fabricated across sizable areas. While these devices target non-volatile or ultra-low-leakage applications rather than high-speed logic, they show that graphene-based components can be patterned, suspended, and integrated in ways that move beyond isolated test structures.
Bringing these strands together will require hybrid process flows. One plausible path is to use top-down patterning for most wiring and device features, reserving bottom-up growth or transfer for critical active regions where atomic precision pays the biggest dividends. Another is to exploit the vertical transistor geometries enabled by graphene electrodes, stacking logic, memory, and photonic layers without the thermal and lattice constraints of conventional three-dimensional integration.
For now, graphene’s most advanced transistors and optical switches live in specialized laboratories, not commercial fabs. Yet the progress across channel engineering, vertical architectures, and ultrafast photonics suggests that graphene is moving from a material of promise to one with a concrete, if complex, roadmap. If researchers can solve the remaining challenges of large-area patterning, alignment, and contact resistance, the sub-nanometer ribbons, 4-nm vertical stacks, and femtosecond switches demonstrated today could underpin a new class of ultra-efficient processors tomorrow.
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*This article was researched with the help of AI, with human editors creating the final content.
