A magnetic tunnel junction engineered to produce four distinct resistance states instead of the standard two could double the data density of spintronic memory without requiring additional physical space or significant extra energy. The device, built from layered ferromagnetic films on a tantalum underlayer, uses spin-orbit torques to switch between all four states without an external magnetic field. The result challenges a longstanding assumption in memory design: that packing more bits per cell demands exotic materials or complex multi-device architectures.
How Four States Emerge From One Junction
Conventional magnetic tunnel junctions store a single bit by toggling between two resistance levels, corresponding to parallel and antiparallel magnetization of two ferromagnetic layers. The new device breaks that limit through geometry. Its architecture pairs a single elliptical ferromagnetic layer with a second layer shaped as two crossing ellipses, creating four remanent magnetic configurations rather than two. Each configuration produces a measurably different resistance when current tunnels through the barrier, giving the cell four stable readout levels.
In this layout, the crossing ellipses introduce multiple easy axes for magnetization, so the relative orientation between the free and reference layers is not simply “aligned” or “opposed.” Instead, the magnetization can settle into four distinct angular relationships, each corresponding to a different tunneling probability. Careful engineering of the anisotropy and shape ensures that these configurations are energetically separated enough to remain stable at room temperature, yet close enough that current-induced torques can reliably move the system from one state to another.
Switching between those states relies on spin-orbit torques generated in the tantalum layer beneath the stack. Because the torques act directly on the magnetization, the device does not need an external magnetic field to toggle between any pair of states. That field-free operation, described in the preprint version of the same work, matters for integration with standard semiconductor fabrication, where stray magnetic fields complicate chip-level design. The practical upshot is that each memory cell stores two bits of data in the footprint that normally holds one.
Earlier Routes to Four-State Memory
The idea of encoding more than one bit in a single tunnel junction is not new, but earlier approaches relied on different physical mechanisms and faced distinct trade-offs. One line of research combined tunneling magnetoresistance with tunneling electroresistance in a ferroelectric barrier spin-valve, toggling between states using voltage pulses for electroresistance and magnetic configuration for magnetoresistance. That approach demonstrated a genuine four-state memory concept, yet it required a ferroelectric barrier material, adding fabrication complexity and compatibility questions for mainstream CMOS processes.
A separate effort used a multiferroic tunnel junction built from NiFe, BaTiO3, and LSMO layers to achieve low-field switching in a four-state nonvolatile memory. That work emphasized a reduced switching field and reported OFF/ON resistance ratios and tunneling magnetoresistance values, but the oxide materials involved are difficult to integrate with silicon-based manufacturing lines and often demand specialized growth conditions. A third path, demonstrated in a double-pinned perpendicular MTJ spin-valve fabricated on 12-inch wafer sputtering tools, showed four-level resistance behavior in a multi-level perpendicular spin-transfer-torque MRAM concept. That study reported distinct resistance plateaus and confirmed that multi-level operation can be realized using industry-standard deposition and patterning, though it still relied on spin-transfer torque rather than spin-orbit torque for switching.
What sets the newer spin-orbit-torque approach apart is its simpler materials stack. Tantalum is already a workhorse metal in semiconductor fabs, and the ferromagnetic layers use conventional alloys shaped by lithography rather than exotic crystal growth. The engineering challenge shifts from discovering new compounds to refining nanoscale patterning and current routing, domains where chipmakers already have deep expertise. By avoiding ferroelectrics or complex oxides, the design aims to slot into existing MRAM process flows with minimal disruption.
Fresh Evidence From Oxide Bilayers
A separate preprint posted in March 2026 adds another data point to the four-state memory effort. Researchers reported a SrIrO3/SrRuO3 bilayer exhibiting four intrinsically stable magnetic states that are electrically distinguishable, with switching driven by spin-orbit torque and the material’s own magnetic anisotropy. The team mapped a transition protocol among all states and provided in-situ NV-center magnetometry evidence confirming each configuration. While the oxide bilayer system differs from the metallic MTJ approach, it reinforces the broader principle: careful engineering of anisotropy and symmetry can unlock multistate behavior without stacking multiple devices in series or parallel.
The NV-center magnetometry technique used in that work also signals a maturing toolkit for characterizing spintronic memory at the nanoscale. Quantum defects in diamond can sense local magnetic fields with high spatial resolution, allowing researchers to visualize domain structures and switching pathways in operando. As devices shrink and the resistance gaps between states narrow, precision measurement tools become just as important as the memory cells themselves, both for basic understanding and for process control during manufacturing.
Why Binary Assumptions Hold Back Density
Most commercial MRAM products treat each cell as a binary switch. That design choice simplifies read and write circuits but caps storage density at one bit per junction. Doubling capacity has traditionally meant shrinking cells or stacking layers, both of which hit physical and economic limits as feature sizes approach single-digit nanometers. A four-state cell sidesteps that wall by extracting more information from the same physical footprint, effectively doubling capacity without pushing lithography to new extremes.
The catch is read margin. Distinguishing four resistance levels demands tighter sensing tolerances than distinguishing two. Noise, temperature drift, and manufacturing variation all eat into the gap between adjacent states. The IEDM literature on perpendicular MTJ scaling has documented these challenges for years, highlighting how variability in barrier thickness, interfacial roughness, and magnetic anisotropy can blur resistance distributions. Any practical four-state MRAM will need sense amplifiers tuned to smaller resistance windows, and that circuit overhead, along with more sophisticated error-correction schemes, could offset some of the density gains.
Write reliability poses another constraint. In a binary MTJ, a failed write typically leaves the cell in the original state, which error-correcting codes can often handle. In a four-level system, an incomplete or overshoot write may land the junction in an adjacent state rather than the intended one, complicating error models. Designers must balance pulse amplitude, duration, and direction to guarantee that each operation moves the magnetization cleanly between well-defined minima in the energy landscape.
Thermal stability is closely linked to this problem. To maintain nonvolatility, each magnetic state needs a sufficiently high energy barrier against spontaneous reversal over the device’s lifetime. But if those barriers become too high, switching currents and power consumption rise. Multistate designs must carve out a narrow operating window where all four configurations are both robust and switchable, a more delicate optimization than in binary cells.
From Laboratory Prototypes to Practical Memory
Despite these hurdles, the appeal of four-state spintronic memory remains strong. Doubling per-cell capacity without adding layers could simplify future cache hierarchies and embedded memory blocks, especially in systems where area is at a premium. Spin-orbit-torque operation further promises lower write energy and improved endurance compared with conventional spin-transfer-torque MRAM, easing concerns about wear-out under frequent updates.
Moving from prototype demonstrations to products will require coordinated progress on several fronts. Materials scientists must refine stacks that combine robust multistate behavior with CMOS compatibility. Device engineers need to optimize junction shapes, aspect ratios, and current paths to maximize resistance separation among states. Circuit designers will have to develop compact, low-noise sense amplifiers and write drivers capable of steering cells through complex state diagrams without sacrificing speed.
Standardization will matter as well. Just as binary MRAM benefited from agreed-upon metrics for retention, endurance, and switching energy, multilevel spintronic memories will need shared benchmarks for state separability, error rates, and tolerance to process variation. Techniques like NV-center magnetometry and other advanced probes can help establish those standards by providing independent verification of magnetic configurations and transition pathways.
Ultimately, the shift from two-state to four-state operation in a single magnetic tunnel junction is less a radical reinvention than a logical extension of spintronics. By treating magnetization as a richer degree of freedom rather than a simple on–off toggle, researchers are beginning to tap information capacity that has always been present in the physics but underused in products. Whether metallic MTJs, oxide bilayers, or yet-to-be-discovered materials win out, the trajectory is clear: future nonvolatile memories will be judged not only by how small their cells are, but by how many reliable states each cell can sustain and how efficiently electronics can tell them apart.
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*This article was researched with the help of AI, with human editors creating the final content.
