A team of Chinese researchers has built a ferroelectric transistor with a gate length of just 1 nanometer that runs on 0.6 volts, a fraction of the voltage required by today’s commercial chip architectures. Published in the peer-reviewed journal Science Advances, the work targets one of the most pressing bottlenecks in artificial intelligence hardware: the enormous power consumption of memory-intensive operations. If the lab results hold up at scale, the design could reshape how engineers think about energy efficiency in AI processors and edge devices.
What the Transistor Actually Does
The device is a ferroelectric field-effect transistor, or FeFET, that pairs a molybdenum disulfide channel with a metallic single-walled carbon nanotube gate electrode. That combination allows the transistor to switch states at just 0.6 V, well below the operating voltages typical of leading-edge silicon nodes. Lower voltage translates directly into lower dynamic power dissipation, the dominant source of heat and energy waste in dense chip designs.
Two performance numbers stand out. The transistor achieves a current on/off ratio of roughly 2 × 106, meaning it can distinguish sharply between its “on” and “off” states, a quality essential for reliable memory storage. Its programming speed of 1.6 nanoseconds puts it in the same ballpark as fast SRAM, though in a non-volatile package that retains data without continuous power. Together, these metrics suggest a device that could serve double duty as both logic and memory, collapsing the gap between processing and storage that slows conventional chip architectures.
Ferroelectric behavior is key to this dual role. In a FeFET, the gate stack includes a ferroelectric material whose internal polarization can be flipped by an electric field and then remain stable after the field is removed. That remnant polarization shifts the channel’s threshold voltage, effectively encoding a digital “0” or “1.” Because the polarization state persists without power, the transistor can act as a non-volatile memory cell, while still switching quickly enough to participate in logic operations.
Tackling the Memory Wall in AI Hardware
Modern AI workloads, from large language models to real-time image recognition, spend most of their energy shuttling data between processors and memory. Engineers call this the “memory wall” or “power wall,” a fundamental limitation rooted in the von Neumann architecture that separates computation from storage. The National Natural Science Foundation of China framed the new transistor as a direct response to that bottleneck, describing the underlying physics as a “nanogate electric-field enhancement mechanism” that concentrates switching energy at atomic scales.
The practical implication is significant. A transistor that can store and process information in the same physical location, at low voltage and high speed, could reduce the constant data transfers that account for a large share of power consumption in AI accelerators. Data centers running inference on billions of parameters stand to benefit most, because every millivolt saved per transistor multiplies across billions of devices on a single chip. Edge devices, which must perform on-device inference under tight thermal and battery constraints, could also gain from embedding memory directly into compute arrays.
Architectures built around such FeFETs might resemble today’s compute-in-memory designs, where matrix multiplications are performed inside memory arrays instead of on separate logic cores. In principle, the strong on/off ratio and nanosecond-scale switching demonstrated here could support dense crossbar arrays that both store model weights and perform multiply-accumulate operations, cutting down on off-chip memory traffic that currently dominates AI energy budgets.
Who Built It and How
According to a Peking University release, the research team includes Qiu Chenguang, identified as a senior researcher, and Peng Lianmao, described as an academician of the Chinese Academy. The sources do not single out one principal investigator; both figures appear in leadership roles on the project. The work was funded under a major NSFC research plan focused on surface and interface science for future technologies, though the public materials do not list specific grant amounts.
The university statement also claims the fabrication process is compatible with standard semiconductor manufacturing workflows. That would be a meaningful differentiator if confirmed. Many experimental transistors at the sub-nanometer scale rely on bespoke assembly techniques, such as manual placement of nanowires or low-throughput deposition steps, that cannot be replicated in a commercial foundry. By contrast, the Peking University team points to process steps that they say align with mainstream CMOS tooling, suggesting a shorter path from lab demonstration to pilot production.
Still, “compatibility” can mean different things. Matching basic materials and process temperatures is not the same as demonstrating that the device can survive the full complexity of a modern logic or memory stack, including multilayer interconnects, packaging, and reliability screening. The current reports stop at single-device fabrication and characterization, leaving open questions about how the technology would integrate into existing process design kits or design rules.
Why the 0.6 V Threshold Matters
Voltage is the single most powerful lever for cutting chip power consumption. Dynamic power scales with the square of the supply voltage, so halving voltage reduces dynamic power by roughly 75 percent, all else equal. Current commercial logic transistors at the most advanced nodes typically operate above 0.7 V. A device that functions reliably at 0.6 V while maintaining strong on/off contrast and nanosecond-class switching speed would represent a meaningful step down the voltage curve.
For AI-specific hardware, the savings compound. Training runs for frontier models now consume megawatt-hours of electricity, and inference at the edge—in phones, cameras, and autonomous vehicles—is constrained by battery capacity and cooling budgets. A low-voltage, non-volatile memory element that eliminates the need for constant refresh cycles could extend battery life and reduce thermal design requirements simultaneously. In data centers, even incremental reductions in per-operation energy can translate into lower operating costs and a smaller carbon footprint when multiplied across millions of accelerators.
The transistor’s ferroelectric nature also helps at low voltage because the internal polarization can amplify the effective electric field at the channel interface. This “negative capacitance” effect, closely related to the nanogate electric-field enhancement described by the NSFC, can steepen the subthreshold slope and allow transistors to switch sharply even when the external supply voltage is reduced. If that behavior proves stable over time and across temperature, it could offer a path to further voltage scaling beyond what conventional MOSFETs allow.
What the Research Does Not Prove
The published article contains no data on multi-device integration, endurance cycling over millions or billions of write operations, or performance under the thermal loads typical of a packaged chip. These are standard gaps in early-stage transistor research, but they matter because the headline claims—sub-1 nm gate length and ultralow voltage—have historically proven difficult to sustain when devices are packed at commercial densities and operated continuously.
No independent benchmark comparisons against competing architectures from major foundries have been published alongside this work. That absence is not unusual for an academic paper, which typically focuses on device physics rather than system-level metrics. It does mean, however, that readers should treat the reported on/off ratio and programming speed as promising indicators rather than definitive proof of commercial superiority. Real-world chip performance depends on many additional variables, including interconnect resistance, parasitic capacitances, leakage in peripheral circuits, and the overhead of error-correction schemes.
There is also no publicly available raw experimental dataset for independent replication. The paper’s abstract and supplementary materials provide summary statistics and representative device curves, but full measurement logs and wafer maps have not been released. For a claim this significant, third-party reproduction will be essential before industry can seriously contemplate adoption. Variability across devices, sensitivity to process deviations, and long-term drift under bias stress are all potential failure modes that only large-sample studies can uncover.
Another open question is endurance. Ferroelectric materials can suffer from fatigue, imprint, and retention loss after repeated switching. Without data on how the FeFET behaves after millions of program-erase cycles, it is impossible to know whether it is better suited to roles resembling flash memory, configuration storage, or high-write-intensity AI workloads such as on-chip training or continual learning. Similarly, the impact of radiation, humidity, and packaging-induced stress on the ultrashort 1 nm gate region has not yet been characterized.
What Comes Next
To move from a headline-grabbing prototype to a viable technology platform, the research community will need to demonstrate arrays of these FeFETs operating together, along with peripheral circuitry that can address, program, and read them at scale. That includes showing uniform behavior across large areas, quantifying yield, and validating endurance and retention under realistic operating conditions. Collaboration with commercial foundries could help test whether the claimed process compatibility holds up when subjected to high-volume manufacturing constraints.
Even if many of these hurdles remain, the work highlights a broader trend: pushing computation closer to where data resides, and doing so at ever lower voltages. By pairing a one-nanometer ferroelectric gate with a low-power channel material, the Peking University team has sketched one possible path beyond the limits of conventional CMOS scaling. Whether this particular device architecture becomes a commercial product or not, the concepts it embodies (compute-in-memory, non-volatile logic, and aggressive voltage reduction) are likely to shape the next generation of AI hardware research.
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*This article was researched with the help of AI, with human editors creating the final content.
