Most of the energy an AI chip burns never goes toward actual computation. It goes toward moving data: shuttling model weights and activations back and forth between memory banks and processing cores across metal wires that, at modern scales, act like tiny resistive heaters. Engineers have a name for this penalty, the “memory wall,” and it has become the defining bottleneck for edge AI hardware, where power budgets are tight and every milliwatt counts.
A research team at the Institute of Science Tokyo, working with semiconductor equipment maker Canon ANELVA, believes it has a building block that could chip away at that wall. In a paper published in Advanced Electronic Materials titled “Thickness Scaling of Integrated Pt/(Al0.9Sc0.1)N/Pt Capacitor Stacks to 30 nm,” the group demonstrated a ferroelectric capacitor stack, electrodes included, thinned to roughly 30 nanometers while still switching reliably. That is thin enough to sit inside the wiring layers above a chip’s transistors, storing data right where it gets processed.
Why 30 nanometers changes the math
Previous ferroelectric memory demonstrations often quoted only the thickness of the active layer, the slice of material that actually stores a data bit. The electrodes and buffer layers that sandwich it added bulk, making the full device too tall to squeeze into the back-end-of-line (BEOL) metal stack of a modern logic chip without disrupting the layers above.
At 30 nm for the complete stack, that constraint loosens. The capacitor can plausibly nest between existing copper interconnect layers, opening the door to three-dimensional integration where memory cells sit directly over compute blocks and talk through short vertical vias instead of long horizontal wires. The shorter the path, the less energy each data fetch costs.
In conventional AI accelerators, even on-chip SRAM occupies real estate beside the compute array, and every read or write must traverse routing channels that toggle at high frequency. A dense blanket of non-volatile ferroelectric capacitors stacked above the logic could serve as a near-memory cache for neural network weights, cutting both the distance and the frequency of data movement. The thinner each cell, the more of them can be packed close to the hottest compute regions without violating design rules.
The material: aluminum scandium nitride
The ferroelectric layer in the stack is aluminum scandium nitride (AlScN), a material that has gained traction in the semiconductor research community over the past several years. Aluminum nitride already appears in RF filters and piezoelectric sensors, and doping it with scandium unlocks ferroelectric polarization, the ability to hold a stable, switchable charge state that represents a stored bit.
AlScN’s appeal for chipmakers is partly practical. Because aluminum nitride deposition tools already exist in fabs, adapting them for scandium-doped films requires incremental rather than revolutionary changes. Canon ANELVA, which manufactures physical vapor deposition systems used across the semiconductor industry, collaborated on the 30-nm work, according to the Institute of Science Tokyo’s project announcement. That partnership suggests the deposition recipes are being developed with volume manufacturing in mind, though neither party has disclosed yield data, wafer-scale uniformity numbers, or a production timeline.
A separate study published in Nature Communications explored AlScN in a different device geometry, ferroelectric thin-film transistors built from AlScN/AlN/AlScN stacks, and showed that engineers can decouple polarization strength from the coercive field. That matters because it means switching voltage and data retention can be tuned somewhat independently, a flexibility that plagued earlier ferroelectric candidates like lead zirconate titanate (PZT). The transistor work used a different architecture than the 30-nm capacitor, but it reinforces the idea that AlScN is versatile enough to serve multiple roles in a tightly integrated chip.
Quantifying the payoff of keeping data local
The performance case for embedded memory does not rest on the AlScN work alone. A study published in Nature Electronics on a spintronic compute-in-memory macro built from STT-MRAM measured what happens when computation occurs inside the memory array itself. The design achieved energy efficiency gains measured in tera-operations per second per watt (TOPS/W), a standard metric for AI hardware, by eliminating the data transfers that dominate power consumption in conventional architectures.
That experiment used a different memory technology and a different integration approach, so its specific numbers cannot be pasted onto an AlScN-based design. But the underlying physics is the same: shorter wires, fewer data moves, less wasted energy. The TOPS/W framework it established gives chip architects a concrete target for what any embedded memory solution, ferroelectric or otherwise, should aim to deliver.
What has not been proven yet
The 30-nm capacitor stack is a device-level demonstration, not a chip-level one. No published data show it operating inside a complete AI accelerator. The Advanced Electronic Materials paper reports materials characterization and switching metrics under controlled lab conditions; it does not include system-level benchmarks such as inference latency or energy savings on a real neural network workload.
Bridging that gap involves a long list of engineering challenges. The capacitors must be integrated with CMOS transistors, survive the thermal budgets of back-end processing, and perform reliably amid the simultaneous switching noise, temperature gradients, and voltage droop of a working chip. Stray capacitances and parasitic resistances can distort the clean hysteresis loops measured in the lab.
Long-term endurance is another open question. The Advanced Electronic Materials data indicate stable switching at 30 nm, suggesting that depolarization fields and leakage have not yet overwhelmed the ferroelectric behavior. But realistic AI workloads can demand billions of write cycles over a product’s lifetime, and no published cycling data at that scale exist for this stack as of April 2026.
Then there are the economics. Without public figures on yield, variability, or cost per device, it is impossible to judge whether AlScN capacitors can compete on price with established embedded memory options that already have mature supply chains.
A crowded field of contenders
The AlScN stack is not the only technology vying to put memory closer to AI compute. STT-MRAM, the technology behind the Nature Electronics macro, already ships in select edge processors and benefits from a relatively mature manufacturing ecosystem. SRAM remains unmatched for raw access speed and dominates on-chip caches today. Embedded flash serves microcontrollers that store model weights once and rarely rewrite them.
Perhaps the most direct competitor is hafnium zirconium oxide (HZO), another ferroelectric material that has attracted heavy investment from major foundries. HZO can be deposited using atomic layer deposition tools already present in advanced fabs, and multiple research groups have demonstrated HZO-based ferroelectric memories integrated into BEOL stacks. AlScN’s potential advantages, including higher polarization and compatibility with sputtering tools, will need to be weighed against HZO’s head start in integration maturity.
Any new entrant must carve out a niche where its combination of density, write energy, endurance, and integration simplicity justifies the risk of adopting a less proven material. For AlScN, that niche may lie in applications where high polarization at very thin dimensions is critical, exactly the regime the 30-nm demonstration targets.
How software fits into the picture
Even if the hardware works, system architects will need to decide how to expose embedded ferroelectric memory to the software stack. It could appear as a fast non-volatile cache for model weights, as a scratchpad for intermediate activations, or as part of a more radical compute-in-memory array where multiply-accumulate operations happen directly on stored data. Each approach implies different demands for endurance, access patterns, and error correction, shaping the acceptable operating window for the AlScN devices.
That co-design challenge is not unique to ferroelectric memory. It applies to every emerging memory technology, and it is often where promising lab results stall on the road to products. The teams that succeed tend to be the ones that involve circuit designers and software engineers early, rather than optimizing the memory cell in isolation and hoping the rest of the stack adapts.
Where this stands in April 2026
The 30-nm Pt/AlScN/Pt capacitor stack from the Institute of Science Tokyo is a credible, peer-reviewed advance in ferroelectric scaling. It addresses the right problem, data movement as the dominant energy cost in AI hardware, and it does so in a form factor that could mesh with advanced logic processes. The collaboration with Canon ANELVA adds a layer of industrial plausibility that pure academic demonstrations often lack.
But the distance between a working capacitor and a shipping AI chip is measured in years and billions of dollars of process development. What remains missing are demonstrations of full CMOS integration, endurance data under realistic workloads, yield and cost metrics, and the architectural co-design that turns a memory element into a system-level advantage. A summary of the research on Phys.org captures the team’s ambitions, but the peer-reviewed literature is where the technical evidence lives.
For now, the 30-nm stack is best understood as a promising building block, not a finished product. It joins a growing portfolio of embedded memory candidates that collectively signal a shift in how the semiconductor industry thinks about AI chip design: less about faster transistors, more about smarter data placement.
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*This article was researched with the help of AI, with human editors creating the final content.
